From 88b6ef9a187a34d6fb512e9c83c9727bc3c0fa78 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 7 Mar 2011 10:56:14 -0800 Subject: u2/u2p: proper connections for dsp_framer --- usrp2/fifo/dsp_framer36.v | 1 - usrp2/vrt/vita_rx_chain.v | 3 +++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'usrp2') diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index d99b1fcaf..c2ae8f96c 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -13,7 +13,6 @@ module dsp_framer36 wire do_xfer_in = dfifo_in_src_rdy & dfifo_in_dst_rdy; wire do_xfer_out = src_rdy_o & dst_rdy_i; - // dfifo_out_src_rdy & dfifo_out_dst_rdy; wire have_space = dfifo_in_dst_rdy & tfifo_in_dst_rdy; reg [15:0] pkt_len_in, pkt_len_out; diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index 2410dcc37..d7498286d 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -13,6 +13,9 @@ module vita_rx_chain wire [100:0] sample_data; wire sample_dst_rdy, sample_src_rdy; wire [31:0] vrc_debug, vrf_debug; + + wire [35:0] rx_data_int; + wire rx_src_rdy_int, rx_dst_rdy_in; vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control (.clk(clk), .reset(reset), .clear(clear), -- cgit v1.2.3