From 4e5f4e137e70728116536ac19f1bf946fa890b7d Mon Sep 17 00:00:00 2001
From: Ian Buckley <ian.buckley@gmail.com>
Date: Wed, 10 Nov 2010 09:45:12 -0800
Subject: 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZ
which allows the SRAM to be placed in a sleep mode. This pin was erroniously
pulled high at the top level rendering the SRAM unusable.
2) Added declaration for extramfifo debug bus which had got deleted
at some point in the past
3) Created a debug bundle of signals from extsramfifo to help diagnose
problem 1)
4) u2p Rev1 PCB ommits control of any of the SRAM chip selects. Made a
code change so that control logic does not rely on the presence of this
pin and ensuring that the SRAM is always placed in READ mode in any idle cycles.
---
usrp2/extramfifo/ext_fifo.v | 12 ++++++------
usrp2/extramfifo/nobl_if.v | 9 ++++++---
usrp2/top/u2plus/u2plus.v | 3 ++-
usrp2/top/u2plus/u2plus_core.v | 4 +++-
4 files changed, 17 insertions(+), 11 deletions(-)
(limited to 'usrp2')
diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v
index 2a8d57448..44229f846 100644
--- a/usrp2/extramfifo/ext_fifo.v
+++ b/usrp2/extramfifo/ext_fifo.v
@@ -46,8 +46,6 @@ module ext_fifo
wire [EXT_WIDTH-1:0] read_data;
wire full1, empty1;
wire almost_full2, full2, empty2;
- wire [INT_WIDTH-1:0] data_to_fifo;
- wire [INT_WIDTH-1:0] data_from_fifo;
wire [FIFO_DEPTH-1:0] capacity;
wire space_avail;
wire data_avail;
@@ -151,12 +149,14 @@ module ext_fifo
- always @ (posedge int_clk)
- debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
+// always @ (posedge int_clk)
+// debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
always @ (posedge ext_clk)
- debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
-
+ // debug[27:0] <= {RAM_WEn,RAM_CE1n,RAM_A[3:0],read_data[17:0],empty1,space_avail,data_avail,almost_full2 };
+ debug[31:0] <= {7'h0,src_rdy_i,read_input_fifo,write_output_fifo,dst_rdy_i,full2,almost_full2,empty2,full1,empty1,write_data[7:0],read_data[7:0]};
+
+
always@ (posedge ext_clk)
// debug2[31:0] <= {write_data[15:0],read_data[15:0]};
debug2[31:0] <= 0;
diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v
index 391a841e8..7ff7eaa03 100644
--- a/usrp2/extramfifo/nobl_if.v
+++ b/usrp2/extramfifo/nobl_if.v
@@ -50,18 +50,21 @@ module nobl_if
address_pipe1 <= 0;
write_pipe1 <= 0;
data_out_pipe1 <= 0;
+ RAM_WEn <= 1;
+ RAM_CE1n <= 1;
+
end
else
begin
enable_pipe1 <= enable;
- RAM_CE1n <= ~enable; // Creates IOB flob
-
+ RAM_CE1n <= ~enable; // Creates IOB flop
+ RAM_WEn <= ~write; // Creates IOB flop
if (enable)
begin
address_pipe1 <= address;
write_pipe1 <= write;
- RAM_WEn <= ~write; // Creates IOB flob
+// RAM_WEn <= ~write; // Creates IOB flop
if (write)
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index 5396ae6cd..d4a681731 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -486,7 +486,8 @@ module u2plus
.spiflash_mosi (flash_mosi)
);
- assign RAM_ZZ = 1;
+ // Drive low so that RAM does not sleep.
+ assign RAM_ZZ = 0;
// Byte Writes are qualified by the global write enable
// Always do 36bit operations to extram.
assign RAM_BWn = 4'b0000;
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v
index 9b177390a..081ffe4c6 100644
--- a/usrp2/top/u2plus/u2plus_core.v
+++ b/usrp2/top/u2plus/u2plus_core.v
@@ -164,7 +164,9 @@ module u2plus_core
wire [31:0] atr_lines;
wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
- debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp;
+ debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp,
+ debug_extfifo;
+
wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
--
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