From 21c3765da33652ec186e230d2aabc52625e32d7f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 15 Dec 2010 17:17:11 -0800 Subject: now supports up to 4 different udp ports --- usrp2/udp/prot_eng_tx.v | 39 ++++++++++++++++++++++++++------------- usrp2/udp/prot_eng_tx_tb.v | 27 +++++++++++++++++---------- 2 files changed, 43 insertions(+), 23 deletions(-) (limited to 'usrp2') diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index a18eb73ae..06ae166ba 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -7,6 +7,7 @@ // Odd means the last word is half full // Flags[1:0] is {eop, sop} // Protocol word format is: +// 20 UDP Port Here // 19 Last Header Line // 18 IP Header Checksum XOR // 17 IP Length Here @@ -34,13 +35,18 @@ module prot_eng_tx assign dst_rdy_o = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30)); assign src_rdy_o = src_rdy_i & ~((state==0) | (state==1) | (state==30)); - localparam HDR_WIDTH = 16 + 4; // 16 bits plus flags + localparam HDR_WIDTH = 16 + 5; // 16 bits plus flags localparam HDR_LEN = 32; // Up to 64 bytes of protocol // Store header values in a small dual-port (distributed) ram reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1]; wire [HDR_WIDTH-1:0] header_word; - reg [15:0] chk_precompute; + + reg [1:0] port_sel; + reg [15:0] per_port_data[0:3]; + reg [15:0] udp_port, chk_precompute; + + always @(posedge clk) udp_port <= per_port_data[port_sel]; always @(posedge clk) if(set_stb & ((set_addr & 8'hE0) == BASE)) @@ -49,13 +55,18 @@ module prot_eng_tx if(set_data[18]) chk_precompute <= set_data[15:0]; end - - assign header_word = header_ram[state]; + always @(posedge clk) + if(set_stb & ((set_addr & 8'hFC) == (BASE+24))) + per_port_data[set_addr[1:0]] <= set_data; + + wire do_udp_port = header_word[20]; wire last_hdr_line = header_word[19]; - wire ip_chk = header_word[18]; - wire ip_len = header_word[17]; - wire udp_len = header_word[16]; + wire do_ip_chk = header_word[18]; + wire do_ip_len = header_word[17]; + wire do_udp_len = header_word[16]; + + assign header_word = header_ram[state]; // Protocol State Machine reg [15:0] length; @@ -75,6 +86,7 @@ module prot_eng_tx 0 : begin fast_path <= datain[0]; + port_sel <= datain[2:1]; state <= 1; end 1 : @@ -113,15 +125,16 @@ module prot_eng_tx checksum_reg <= checksum; always @* - if(ip_chk) - //dataout_int <= header_word[15:0] ^ ip_length; + if(do_payload) + dataout_int <= datain[15:0]; + else if(do_ip_chk) dataout_int <= 16'hFFFF ^ checksum_reg; - else if(ip_len) + else if(do_ip_len) dataout_int <= ip_length; - else if(udp_len) + else if(do_udp_len) dataout_int <= udp_length; - else if(do_payload) - dataout_int <= datain[15:0]; + else if(do_udp_port) + dataout_int <= udp_port; else dataout_int <= header_word[15:0]; diff --git a/usrp2/udp/prot_eng_tx_tb.v b/usrp2/udp/prot_eng_tx_tb.v index e7ffeb5e1..c8fffe605 100644 --- a/usrp2/udp/prot_eng_tx_tb.v +++ b/usrp2/udp/prot_eng_tx_tb.v @@ -80,7 +80,7 @@ module prot_eng_tx_tb(); begin count <= 4; src_rdy_f36i <= 1; - f36_data <= 32'h0001_000c; + f36_data <= 32'h0003_000c; f36_sof <= 1; f36_eof <= 0; f36_occ <= 0; @@ -140,16 +140,23 @@ module prot_eng_tx_tb(); @(negedge rst); @(posedge clk); WriteSREG(BASE, {12'b0, 4'h0, 16'h0000}); - WriteSREG(BASE+1, {12'b0, 4'h0, 16'h0000}); - WriteSREG(BASE+2, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+3, {12'b0, 4'h0, 16'h1234}); - WriteSREG(BASE+4, {12'b0, 4'h8, 16'h5678}); - WriteSREG(BASE+5, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+6, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+7, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+8, {12'b0, 4'h0, 16'hABCD}); - WriteSREG(BASE+9, {12'b0, 4'h0, 16'hABCD}); + WriteSREG(BASE+1, {11'b0, 5'h00, 16'h0000}); + WriteSREG(BASE+2, {11'b0, 5'h00, 16'hABCD}); + WriteSREG(BASE+3, {11'b0, 5'h00, 16'h1234}); + WriteSREG(BASE+4, {11'b0, 5'h00, 16'h5678}); + WriteSREG(BASE+5, {11'b0, 5'h00, 16'hF00D}); + WriteSREG(BASE+6, {11'b0, 5'h00, 16'hBEEF}); + WriteSREG(BASE+7, {11'b0, 5'h10, 16'hDCBA}); + WriteSREG(BASE+8, {11'b0, 5'h00, 16'h4321}); + WriteSREG(BASE+9, {11'b0, 5'h04, 16'hABCD}); + WriteSREG(BASE+10, {11'b0, 5'h08, 16'hABCD}); @(posedge clk); + + WriteSREG(BASE+24, 16'h6666); + WriteSREG(BASE+25, 16'h7777); + WriteSREG(BASE+26, 16'h8888); + WriteSREG(BASE+27, 16'h9999); + PutPacketInFIFO36(32'hA0B0C0D0,16); @(posedge clk); @(posedge clk); -- cgit v1.2.3 From 54588404b0e168d42ca963a282c61fa137612a63 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 15 Dec 2010 17:37:58 -0800 Subject: generate port number headers in the dsp error units --- usrp2/top/u2_rev3/u2_core.v | 3 ++- usrp2/top/u2plus/u2plus_core.v | 3 ++- usrp2/vrt/gen_context_pkt.v | 7 ++++--- usrp2/vrt/vita_tx_chain.v | 7 ++++--- 4 files changed, 12 insertions(+), 8 deletions(-) (limited to 'usrp2') diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 30b47b818..41e308723 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -691,7 +691,8 @@ module u2_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 4e0b190ef..33db2c2d3 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -652,7 +652,8 @@ module u2plus_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 44bb7b548..cc34cceed 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -1,7 +1,8 @@ module gen_context_pkt - #(parameter PROT_ENG_FLAGS=1) + #(parameter PROT_ENG_FLAGS=1, + parameter DSP_NUMBER=0) (input clk, input reset, input clear, input trigger, output sent, input [31:0] streamid, @@ -67,10 +68,10 @@ module gen_context_pkt endcase // case (ctxt_state) assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) ); - + always @* case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 13'b0, DSP_NUMBER[0], 1'b1, 1'b1, 16'd28 }; // UDP port 1 or 3 CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 2ec78189b..6f567668d 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -5,7 +5,8 @@ module vita_tx_chain parameter REPORT_ERROR=0, parameter DO_FLOW_CONTROL=0, parameter PROT_ENG_FLAGS=0, - parameter USE_TRANS_HEADER=0) + parameter USE_TRANS_HEADER=0, + parameter DSP_NUMBER=0) (input clk, input reset, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, @@ -71,7 +72,7 @@ module vita_tx_chain wire [35:0] flow_data, err_data_int; wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int; - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_flow_pkt + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_flow_pkt (.clk(clk), .reset(reset), .clear(clear_vita), .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(32'd0), @@ -82,7 +83,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .packet_consumed(packet_consumed), .trigger(trigger)); - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_tx_err_pkt (.clk(clk), .reset(reset), .clear(clear_vita), .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), -- cgit v1.2.3 From abe10a16e3654eeac3195b344f703ce6f2fa542e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 17 Dec 2010 13:44:40 -0800 Subject: udp_ports: set the source port and destination port from table --- usrp2/udp/prot_eng_tx.v | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'usrp2') diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index 06ae166ba..b86a9950c 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -35,7 +35,7 @@ module prot_eng_tx assign dst_rdy_o = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30)); assign src_rdy_o = src_rdy_i & ~((state==0) | (state==1) | (state==30)); - localparam HDR_WIDTH = 16 + 5; // 16 bits plus flags + localparam HDR_WIDTH = 16 + 6; // 16 bits plus flags localparam HDR_LEN = 32; // Up to 64 bytes of protocol // Store header values in a small dual-port (distributed) ram @@ -43,11 +43,12 @@ module prot_eng_tx wire [HDR_WIDTH-1:0] header_word; reg [1:0] port_sel; - reg [15:0] per_port_data[0:3]; - reg [15:0] udp_port, chk_precompute; + reg [32:0] per_port_data[0:3]; + reg [15:0] udp_src_port, udp_dst_port, chk_precompute; + + always @(posedge clk) udp_src_port <= per_port_data[port_sel][31:16]; + always @(posedge clk) udp_dst_port <= per_port_data[port_sel][15:0]; - always @(posedge clk) udp_port <= per_port_data[port_sel]; - always @(posedge clk) if(set_stb & ((set_addr & 8'hE0) == BASE)) begin @@ -60,11 +61,12 @@ module prot_eng_tx if(set_stb & ((set_addr & 8'hFC) == (BASE+24))) per_port_data[set_addr[1:0]] <= set_data; - wire do_udp_port = header_word[20]; - wire last_hdr_line = header_word[19]; - wire do_ip_chk = header_word[18]; - wire do_ip_len = header_word[17]; - wire do_udp_len = header_word[16]; + wire do_udp_src_port = header_word[21]; + wire do_udp_dst_port = header_word[20]; + wire last_hdr_line = header_word[19]; + wire do_ip_chk = header_word[18]; + wire do_ip_len = header_word[17]; + wire do_udp_len = header_word[16]; assign header_word = header_ram[state]; @@ -133,8 +135,10 @@ module prot_eng_tx dataout_int <= ip_length; else if(do_udp_len) dataout_int <= udp_length; - else if(do_udp_port) - dataout_int <= udp_port; + else if(do_udp_src_port) + dataout_int <= udp_src_port; + else if(do_udp_dst_port) + dataout_int <= udp_dst_port; else dataout_int <= header_word[15:0]; -- cgit v1.2.3 From 6dbdffd226139b3a780f3894a46b844869956571 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 21 Dec 2010 13:27:12 -0800 Subject: don't overwrite checksum values --- usrp2/udp/prot_eng_tx.v | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'usrp2') diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index b86a9950c..76250029c 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -7,7 +7,8 @@ // Odd means the last word is half full // Flags[1:0] is {eop, sop} // Protocol word format is: -// 20 UDP Port Here +// 21 UDP Source Port Here +// 20 UDP Dest Port Here // 19 Last Header Line // 18 IP Header Checksum XOR // 17 IP Length Here @@ -43,7 +44,7 @@ module prot_eng_tx wire [HDR_WIDTH-1:0] header_word; reg [1:0] port_sel; - reg [32:0] per_port_data[0:3]; + reg [31:0] per_port_data[0:3]; reg [15:0] udp_src_port, udp_dst_port, chk_precompute; always @(posedge clk) udp_src_port <= per_port_data[port_sel][31:16]; @@ -51,11 +52,11 @@ module prot_eng_tx always @(posedge clk) if(set_stb & ((set_addr & 8'hE0) == BASE)) - begin - header_ram[set_addr[4:0]] <= set_data; - if(set_data[18]) - chk_precompute <= set_data[15:0]; - end + header_ram[set_addr[4:0]] <= set_data; + + always @(posedge clk) + if(set_stb & ((set_addr[4:0] & 8'hE0) == (BASE + 14))) + chk_precompute <= set_data[15:0]; always @(posedge clk) if(set_stb & ((set_addr & 8'hFC) == (BASE+24))) -- cgit v1.2.3 From 64293ea66b52ad00cfc6862d39d0b16f0a1a63b0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 21 Dec 2010 17:27:46 -0800 Subject: udp_ports: fixed address comparison B+14 is comparison --- usrp2/udp/prot_eng_tx.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2') diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index 76250029c..c642842f6 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -55,7 +55,7 @@ module prot_eng_tx header_ram[set_addr[4:0]] <= set_data; always @(posedge clk) - if(set_stb & ((set_addr[4:0] & 8'hE0) == (BASE + 14))) + if(set_stb & (set_addr == (BASE + 14))) chk_precompute <= set_data[15:0]; always @(posedge clk) -- cgit v1.2.3