From d7a3b89d4f7fea444602b0f8ff52029b0efa835f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 3 Jun 2011 16:18:48 -0700 Subject: dsp: added tx_frontend, instantiated in u2/u2p --- usrp2/vrt/vita_tx_chain.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 542968afa..ac9f08fc8 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -29,7 +29,7 @@ module vita_tx_chain input [63:0] vita_time, input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o, output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i, - output [15:0] dac_a, output [15:0] dac_b, + output [23:0] tx_i, output [23:0] tx_q, output underrun, output run, output [31:0] debug); @@ -84,7 +84,7 @@ module vita_tx_chain (.clk(clk),.rst(reset), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample(sample_tx), .run(run), .strobe(strobe_tx), - .dac_a(dac_a),.dac_b(dac_b), + .tx_i(tx_i),.tx_q(tx_q), .debug(debug_tx_dsp) ); wire [35:0] flow_data, err_data_int; -- cgit v1.2.3