From 12755e4e822441b73aad4ca3fdfbb157a3a86477 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 19 Aug 2010 12:46:04 -0700 Subject: Regenerated FIFO with lower trigger level for almost full flag to reflect logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code. --- usrp2/vrt/vita_tx_deframer.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 220d3b061..4d5913b2a 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -70,7 +70,7 @@ module vita_tx_deframer <= 0; end else - if((vita_state == VITA_STORE) & fifo_space) + if((vita_state == VITA_STORE) & fifo_space /* IJB & src_rdy_i*/) if(eop) if(has_trailer_reg) vita_state <= VITA_TRAILER; @@ -168,7 +168,7 @@ module vita_tx_deframer 3: sample_d <= data_i[31:0]; endcase // case (vector_phase) - wire store = (vita_state == VITA_STORE); + wire store = (vita_state == VITA_STORE) /* IJB */ && fifo_space; fifo_short #(.WIDTH(4+64+32*MAXCHAN)) short_tx_q (.clk(clk), .reset(reset), .clear(clear), .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space), -- cgit v1.2.3