From bbbf8778b2924b6e285529d6547bcf471092510a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 16 Jul 2010 16:17:35 -0700 Subject: checkpoint. New context packet generator to report underruns and other errors --- usrp2/vrt/gen_context_pkt.v | 64 +++++++++++++++++++++++++++++++++++++++++++++ usrp2/vrt/vita_tx_chain.v | 43 ++++++++++++++++++++++++++++++ 2 files changed, 107 insertions(+) create mode 100644 usrp2/vrt/gen_context_pkt.v create mode 100644 usrp2/vrt/vita_tx_chain.v (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v new file mode 100644 index 000000000..9e3fcbca8 --- /dev/null +++ b/usrp2/vrt/gen_context_pkt.v @@ -0,0 +1,64 @@ + + +module gen_context_pkt + #(parameter PROT_ENG_FLAGS =1) + (input clk, input reset, input clear, + input trigger, output sent, + input [31:0] streamid, + input [63:0] vita_time, + input [31:0] message, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + localparam CTXT_IDLE = 0; + localparam CTXT_PROT_ENG = 1; + localparam CTXT_HEADER = 2; + localparam CTXT_STREAMID = 3; + localparam CTXT_SECS = 4; + localparam CTXT_TICS = 5; + localparam CTXT_TICS2 = 6; + localparam CTXT_MESSAGE = 7; + localparam CTXT_DONE = 8; + + reg [33:0] data_int; + wire src_rdy_int, dst_rdy_int; + wire [3:0] seqno = 0; + reg [3:0] ctxt_state; + + always @(posedge clk) + if(reset | clear) + ctxt_state <= CTXT_IDLE; + else + case(ctxt_state) + CTXT_IDLE : + if(trigger) + ctxt_state <= CTXT_HEADER; + + CTXT_DONE : + if(~trigger) + ctxt_state <= CTXT_IDLE; + + default : + if(dst_rdy_int) + ctxt_state <= ctxt_state + 1; + endcase // case (ctxt_state) + + assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) ); + + always @* + case(ctxt_state) + CTXT_HEADER : data_int <= { 2'b01, 12'b010100001101, seqno, 16'd6 }; + CTXT_STREAMID : data_int <= { 2'b00, streamid }; + CTXT_SECS : data_int <= { 2'b00, vita_time[63:32] }; + CTXT_TICS : data_int <= { 2'b00, 32'd0 }; + CTXT_TICS2 : data_int <= { 2'b00, vita_time[31:0] }; + CTXT_MESSAGE : data_int <= { 2'b10, message }; + default : {2'b00, 32'b00}; + endcase // case (ctxt_state) + + fifo_short (.WIDTH(34)) ctxt_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); + assign data_o[35:34] = 2'b00; + +endmodule // gen_context_pkt diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v new file mode 100644 index 000000000..17cfe1799 --- /dev/null +++ b/usrp2/vrt/vita_tx_chain.v @@ -0,0 +1,43 @@ + +module vita_tx_chain + #(parameter SR_TX_CTRL=0, + parameter SR_TX_DSP=0) + (input dsp_clk, input dsp_rst, + input set_stb_dsp, input [7:0] set_addr_dsp, input [31:0] set_data_dsp, + input [63:0] vita_time, + input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o, + output [15:0] dac_a, output [15:0] dac_b, + output underrun, output run_tx, + output [31:0] debug); + + wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; + wire [99:0] tx1_data; + wire tx1_src_rdy, tx1_dst_rdy; + wire clear_vita; + wire [31:0] sample_tx; + + vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_vita), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_vita), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time),.underrun(underrun), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug(debug_vtc) ); + + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .dac_a(dac_a),.dac_b(dac_b), + .debug(debug_tx_dsp) ); + + assign debug = debug_vtc | debug_vtd; + +endmodule // vita_tx_chain -- cgit v1.2.3 From 1a85baadf20a7e1a7e2789fd1a8947d27eeea08e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 16 Jul 2010 17:22:57 -0700 Subject: tx error packets now muxed into the ethernet stream back to the host --- usrp2/top/u2_rev3/u2_core_udp.v | 49 ++++++++++++++++++---------------------- usrp2/vrt/Makefile.srcs | 2 ++ usrp2/vrt/gen_context_pkt.v | 12 ++++++---- usrp2/vrt/vita_tx_chain.v | 50 ++++++++++++++++++++++++++++------------- 4 files changed, 66 insertions(+), 47 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index b034791a7..db74188a6 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -466,11 +466,20 @@ module u2_core .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), .debug(debug_udp) ); + wire [35:0] tx_err_data, udp1_tx_data; + wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(dsp_clk), .reset(dsp_reset), .clear(0), + .data0_i(), .src0_rdy_i(), .dst0_rdy_o(), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), @@ -639,40 +648,26 @@ module u2_core // DSP TX wire [35:0] tx_data; - wire [99:0] tx1_data; - wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy; - - wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); - vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), - .debug(debug_vtd) ); - - vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time),.underrun(underrun), - .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug(debug_vtc) ); - - assign debug_vt = debug_vtc | debug_vtd; - - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .tx_data_i(tx_err_data), .tx_src_rdy_i(tx_err_src_rdy), .tx_dst_rdy_o(tx_err_dst_rdy), .dac_a(dac_a),.dac_b(dac_b), - .debug(debug_tx_dsp) ); - + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + assign dsp_rst = wb_rst; // /////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs index 07c62224b..dc4bd8c96 100644 --- a/usrp2/vrt/Makefile.srcs +++ b/usrp2/vrt/Makefile.srcs @@ -10,4 +10,6 @@ vita_rx_control.v \ vita_rx_framer.v \ vita_tx_control.v \ vita_tx_deframer.v \ +vita_tx_chain.v \ +gen_context_pkt.v \ )) diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 9e3fcbca8..2fad43cc6 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -1,7 +1,7 @@ module gen_context_pkt - #(parameter PROT_ENG_FLAGS =1) + #(parameter PROT_ENG_FLAGS=1) (input clk, input reset, input clear, input trigger, output sent, input [31:0] streamid, @@ -23,6 +23,7 @@ module gen_context_pkt wire src_rdy_int, dst_rdy_int; wire [3:0] seqno = 0; reg [3:0] ctxt_state; + reg [63:0] err_time; always @(posedge clk) if(reset | clear) @@ -31,7 +32,10 @@ module gen_context_pkt case(ctxt_state) CTXT_IDLE : if(trigger) - ctxt_state <= CTXT_HEADER; + begin + ctxt_state <= CTXT_HEADER; + err_time <= vita_time; + end CTXT_DONE : if(~trigger) @@ -48,9 +52,9 @@ module gen_context_pkt case(ctxt_state) CTXT_HEADER : data_int <= { 2'b01, 12'b010100001101, seqno, 16'd6 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; - CTXT_SECS : data_int <= { 2'b00, vita_time[63:32] }; + CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; CTXT_TICS : data_int <= { 2'b00, 32'd0 }; - CTXT_TICS2 : data_int <= { 2'b00, vita_time[31:0] }; + CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; CTXT_MESSAGE : data_int <= { 2'b10, message }; default : {2'b00, 32'b00}; endcase // case (ctxt_state) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 17cfe1799..66f775ddf 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -1,13 +1,16 @@ module vita_tx_chain - #(parameter SR_TX_CTRL=0, - parameter SR_TX_DSP=0) - (input dsp_clk, input dsp_rst, - input set_stb_dsp, input [7:0] set_addr_dsp, input [31:0] set_data_dsp, + #(parameter BASE_CTRL=0, + parameter BASE_DSP=0, + parameter REPORT_ERROR=0, + parameter PROT_ENG_FLAGS=0) + (input clk, input reset, + input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o, + input [35:0] err_data_i, input err_src_rdy_i, output err_dst_rdy_o, output [15:0] dac_a, output [15:0] dac_b, - output underrun, output run_tx, + output underrun, output run, output [31:0] debug); wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; @@ -15,29 +18,44 @@ module vita_tx_chain wire tx1_src_rdy, tx1_dst_rdy; wire clear_vita; wire [31:0] sample_tx; + wire [31:0] streamid, message; + wire trigger, sent; - vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_vita), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + setting_reg #(.my_addr(BASE_CTRL+1), .at_reset(0)) sr_streamid + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(streamid),.changed()); + + vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(1)) vita_tx_deframer + (.clk(clk), .reset(reset), .clear(clear_vita), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), .debug(debug_vtd) ); - vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_vita), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32)) vita_tx_control + (.clk(clk), .reset(reset), .clear(clear_vita), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time),.underrun(underrun), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .sample(sample_tx), .run(run), .strobe(strobe_tx), .debug(debug_vtc) ); - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + dsp_core_tx #(.BASE(BASE_DSP)) dsp_core_tx + (.clk(clk),.rst(reset), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample(sample_tx), .run(run), .strobe(strobe_tx), .dac_a(dac_a),.dac_b(dac_b), .debug(debug_tx_dsp) ); + generate + if(REPORT_ERROR==1) + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(underrun), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(message), + .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + endgenerate + assign debug = debug_vtc | debug_vtd; endmodule // vita_tx_chain -- cgit v1.2.3 From 417c1d0abd5cbc52f46f2a3564b6805a59e6fe7f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 16 Jul 2010 17:25:49 -0700 Subject: fix a typo --- usrp2/top/u2_rev3/u2_core_udp.v | 2 +- usrp2/vrt/gen_context_pkt.v | 4 ++-- usrp2/vrt/vita_tx_chain.v | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index db74188a6..74359dad2 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -663,7 +663,7 @@ module u2_core .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .tx_data_i(tx_err_data), .tx_src_rdy_i(tx_err_src_rdy), .tx_dst_rdy_o(tx_err_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(dac_a),.dac_b(dac_b), .underrun(underrun), .run(run_tx), .debug(debug_vt)); diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 2fad43cc6..f413fdd1d 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -56,10 +56,10 @@ module gen_context_pkt CTXT_TICS : data_int <= { 2'b00, 32'd0 }; CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; CTXT_MESSAGE : data_int <= { 2'b10, message }; - default : {2'b00, 32'b00}; + default : data_int <= {2'b00, 32'b00}; endcase // case (ctxt_state) - fifo_short (.WIDTH(34)) ctxt_fifo + fifo_short #(.WIDTH(34)) ctxt_fifo (.clk(clk), .reset(reset), .clear(clear), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 66f775ddf..cc091f2d5 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -8,7 +8,7 @@ module vita_tx_chain input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o, - input [35:0] err_data_i, input err_src_rdy_i, output err_dst_rdy_o, + output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i, output [15:0] dac_a, output [15:0] dac_b, output underrun, output run, output [31:0] debug); -- cgit v1.2.3 From 7934a2be42b417b06504f12232ba590b6e51efde Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 19 Jul 2010 16:20:20 -0700 Subject: move the streamid so it isn't at the same address as clear_state --- usrp2/fifo/fifo36_mux.v | 2 +- usrp2/vrt/vita_tx_chain.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 04ec5abe8..92bf13ff9 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -52,6 +52,6 @@ module fifo36_mux assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0; assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0; assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_0 = (state==MUX_DATA0) ? data0_i : data1_i; + assign data_o = (state==MUX_DATA0) ? data0_i : data1_i; endmodule // fifo36_demux diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index cc091f2d5..84e502b5f 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -21,7 +21,7 @@ module vita_tx_chain wire [31:0] streamid, message; wire trigger, sent; - setting_reg #(.my_addr(BASE_CTRL+1), .at_reset(0)) sr_streamid + setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(streamid),.changed()); -- cgit v1.2.3 From 51c2b19bc6f88f6147d581ed85fa54840e53a97c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 19 Jul 2010 17:58:26 -0700 Subject: insert protocol engine flags when requested --- usrp2/vrt/gen_context_pkt.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index f413fdd1d..780a027ba 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -33,8 +33,11 @@ module gen_context_pkt CTXT_IDLE : if(trigger) begin - ctxt_state <= CTXT_HEADER; err_time <= vita_time; + if(PROT_ENG_FLAGS) + ctxt_state <= CTXT_PROT_ENG; + else + ctxt_state <= CTXT_HEADER; end CTXT_DONE : @@ -50,7 +53,8 @@ module gen_context_pkt always @* case(ctxt_state) - CTXT_HEADER : data_int <= { 2'b01, 12'b010100001101, seqno, 16'd6 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd24 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd6 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; CTXT_TICS : data_int <= { 2'b00, 32'd0 }; -- cgit v1.2.3 From 0cf5dc0aac63940358f13db6f60ef44b55e78a50 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 20 Jul 2010 15:22:19 -0700 Subject: introduce new error types --- usrp2/vrt/vita_tx_chain.v | 33 +++++++++++++++---------- usrp2/vrt/vita_tx_control.v | 57 ++++++++++++++++++++++++++++++++------------ usrp2/vrt/vita_tx_deframer.v | 24 +++++++++++++------ 3 files changed, 80 insertions(+), 34 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 84e502b5f..ad9f11fc6 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -12,30 +12,39 @@ module vita_tx_chain output [15:0] dac_a, output [15:0] dac_b, output underrun, output run, output [31:0] debug); + + localparam MAXCHAN = 1; + localparam FIFOWIDTH = 5+64+(32*MAXCHAN); + + wire [FIFOWIDTH-1:0] tx1_data; + wire tx1_src_rdy, tx1_dst_rdy; + wire clear_vita; + wire [31:0] sample_tx; + wire [31:0] streamid, message; + wire trigger, sent; + wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; + + wire error; + wire [3:0] error_code; - wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; - wire [99:0] tx1_data; - wire tx1_src_rdy, tx1_dst_rdy; - wire clear_vita; - wire [31:0] sample_tx; - wire [31:0] streamid, message; - wire trigger, sent; - + assign underrun = error; + assign message = {28'h0,error_code}; + setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(streamid),.changed()); - vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(1)) vita_tx_deframer + vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer (.clk(clk), .reset(reset), .clear(clear_vita), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), .debug(debug_vtd) ); - vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32)) vita_tx_control + vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control (.clk(clk), .reset(reset), .clear(clear_vita), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time),.underrun(underrun), + .vita_time(vita_time),.error(error),.error_code(error_code), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), .sample(sample_tx), .run(run), .strobe(strobe_tx), .debug(debug_vtc) ); @@ -51,7 +60,7 @@ module vita_tx_chain if(REPORT_ERROR==1) gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(underrun), .sent(), + .trigger(error), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); endgenerate diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index bffc64e52..29d3041b5 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -6,10 +6,11 @@ module vita_tx_control input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, - output underrun, + output reg [3:0] error_code, + output error, // From vita_tx_deframer - input [4+64+WIDTH-1:0] sample_fifo_i, + input [5+64+WIDTH-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, output sample_fifo_dst_rdy_o, @@ -20,14 +21,16 @@ module vita_tx_control output [31:0] debug ); - - assign sample = sample_fifo_i[4+64+WIDTH-1:4+64]; + + assign sample = sample_fifo_i[5+64+WIDTH-1:5+64]; wire [63:0] send_time = sample_fifo_i[63:0]; wire eop = sample_fifo_i[64]; wire eob = sample_fifo_i[65]; wire sob = sample_fifo_i[66]; wire send_at = sample_fifo_i[67]; + wire seqnum_err = sample_fifo_i[68]; + wire now, early, late, too_early; // FIXME ignore too_early for now for timing reasons @@ -41,7 +44,13 @@ module vita_tx_control localparam IBS_RUN = 1; // FIXME do we need this? localparam IBS_CONT_BURST = 2; localparam IBS_UNDERRUN = 3; - localparam IBS_UNDERRUN_DONE = 4; + localparam IBS_TIME_ERROR = 4; + localparam IBS_SEQ_ERROR = 5; + localparam IBS_ERROR_DONE = 7; + + localparam CODE_UNDERRUN = 2; + localparam CODE_SEQ_ERROR = 4; + localparam CODE_TIME_ERROR = 8; reg [2:0] ibs_state; @@ -57,10 +66,12 @@ module vita_tx_control case(ibs_state) IBS_IDLE : if(sample_fifo_src_rdy_i) - if(~send_at | now) + if(seqnum_err) + ibs_state <= IBS_SEQ_ERROR; + else if(~send_at | now) ibs_state <= IBS_RUN; else if(late | too_early) - ibs_state <= IBS_UNDERRUN; + ibs_state <= IBS_TIME_ERROR; IBS_RUN : if(strobe) @@ -74,24 +85,40 @@ module vita_tx_control IBS_CONT_BURST : if(strobe) - ibs_state <= IBS_UNDERRUN_DONE; + ibs_state <= IBS_ERROR_DONE; else if(sample_fifo_src_rdy_i) - ibs_state <= IBS_RUN; + if(seqnum_err) + ibs_state <= IBS_SEQ_ERROR; + else + ibs_state <= IBS_RUN; IBS_UNDERRUN : - if(sample_fifo_src_rdy_i & eop) - ibs_state <= IBS_UNDERRUN_DONE; - - IBS_UNDERRUN_DONE : + begin + error_code <= CODE_UNDERRUN; + if(sample_fifo_src_rdy_i & eop) + ibs_state <= IBS_ERROR_DONE; + end + IBS_TIME_ERROR : + begin + error_code <= CODE_TIME_ERROR; + ibs_state <= IBS_ERROR_DONE; + end + IBS_SEQ_ERROR : + begin + error_code <= CODE_SEQ_ERROR; + ibs_state <= IBS_ERROR_DONE; + end + IBS_ERROR_DONE : ; + endcase // case (ibs_state) assign sample_fifo_dst_rdy_o = (ibs_state == IBS_UNDERRUN) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); - assign underrun = (ibs_state == IBS_UNDERRUN_DONE); + assign error = (ibs_state == IBS_ERROR_DONE); assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, - { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, underrun, ibs_state[2:0] }, + { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, { 8'b0 } }; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 3b95f5902..55869b6e7 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -10,7 +10,7 @@ module vita_tx_deframer input src_rdy_i, output dst_rdy_o, - output [4+64+(32*MAXCHAN)-1:0] sample_fifo_o, + output [5+64+(32*MAXCHAN)-1:0] sample_fifo_o, output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, @@ -21,6 +21,8 @@ module vita_tx_deframer output [31:0] debug ); + localparam FIFOWIDTH = 5+64+(32*MAXCHAN); + wire [1:0] numchan; setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), @@ -36,14 +38,18 @@ module vita_tx_deframer assign is_sob = data_i[25]; assign is_eob = data_i[24]; wire eof = data_i[33]; - reg has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg; reg has_trailer_reg, is_sob_reg, is_eob_reg; - + reg [15:0] pkt_len; reg [1:0] vector_phase; wire line_done; + reg seqnum_err; + reg [3:0] seqnum_reg; + wire [3:0] seqnum = data_i[19:16]; + wire [3:0] next_seqnum = seqnum_reg + 4'd1; + // Output FIFO for packetized data localparam VITA_HEADER = 0; localparam VITA_STREAMID = 1; @@ -61,13 +67,15 @@ module vita_tx_deframer wire eop = eof | (pkt_len==hdr_len); // FIXME would ignoring eof allow larger VITA packets? wire fifo_space; - + always @(posedge clk) if(reset | clear) begin vita_state <= VITA_HEADER; {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} <= 0; + seqnum_err <= 0; + seqnum_reg <= 0; end else if((vita_state == VITA_STORE) & fifo_space) @@ -99,6 +107,8 @@ module vita_tx_deframer vita_state <= VITA_TICS; else vita_state <= VITA_PAYLOAD; + seqnum_reg <= seqnum; + seqnum_err <= ~(is_sob | (seqnum == next_seqnum)); end // case: VITA_HEADER VITA_STREAMID : if(has_classid_reg) @@ -145,7 +155,7 @@ module vita_tx_deframer assign line_done = (vector_phase == numchan); - wire [4+64+32*MAXCHAN-1:0] fifo_i; + wire [FIFOWIDTH-1:0] fifo_i; reg [63:0] send_time; reg [31:0] sample_a, sample_b, sample_c, sample_d; @@ -169,13 +179,13 @@ module vita_tx_deframer endcase // case (vector_phase) wire store = (vita_state == VITA_STORE); - fifo_short #(.WIDTH(4+64+32*MAXCHAN)) short_tx_q + fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q (.clk(clk), .reset(reset), .clear(clear), .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space), .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) ); // sob, eob, has_secs (send_at) ignored on all lines except first - assign fifo_i = {sample_d,sample_c,sample_b,sample_a,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time}; + assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time}; assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ; -- cgit v1.2.3 From a3b53a92d894305e5b319cb325888ab4e686dd05 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 20 Jul 2010 16:50:03 -0700 Subject: cleaner error handling --- usrp2/vrt/vita_tx_control.v | 55 +++++++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 27 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 29d3041b5..f45ba73f1 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -6,8 +6,8 @@ module vita_tx_control input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, - output reg [3:0] error_code, output error, + output reg [3:0] error_code, // From vita_tx_deframer input [5+64+WIDTH-1:0] sample_fifo_i, @@ -43,10 +43,8 @@ module vita_tx_control localparam IBS_IDLE = 0; localparam IBS_RUN = 1; // FIXME do we need this? localparam IBS_CONT_BURST = 2; - localparam IBS_UNDERRUN = 3; - localparam IBS_TIME_ERROR = 4; - localparam IBS_SEQ_ERROR = 5; - localparam IBS_ERROR_DONE = 7; + localparam IBS_ERROR = 3; + localparam IBS_ERROR_DONE = 4; localparam CODE_UNDERRUN = 2; localparam CODE_SEQ_ERROR = 4; @@ -67,16 +65,25 @@ module vita_tx_control IBS_IDLE : if(sample_fifo_src_rdy_i) if(seqnum_err) - ibs_state <= IBS_SEQ_ERROR; + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_SEQ_ERROR; + end else if(~send_at | now) ibs_state <= IBS_RUN; else if(late | too_early) - ibs_state <= IBS_TIME_ERROR; + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_TIME_ERROR; + end IBS_RUN : if(strobe) if(~sample_fifo_src_rdy_i) - ibs_state <= IBS_UNDERRUN; + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_UNDERRUN; + end else if(eop) if(eob) ibs_state <= IBS_IDLE; @@ -85,35 +92,29 @@ module vita_tx_control IBS_CONT_BURST : if(strobe) - ibs_state <= IBS_ERROR_DONE; + begin + ibs_state <= IBS_ERROR_DONE; + error_code <= CODE_UNDERRUN; + end else if(sample_fifo_src_rdy_i) if(seqnum_err) - ibs_state <= IBS_SEQ_ERROR; + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_SEQ_ERROR; + end else ibs_state <= IBS_RUN; - IBS_UNDERRUN : - begin - error_code <= CODE_UNDERRUN; - if(sample_fifo_src_rdy_i & eop) - ibs_state <= IBS_ERROR_DONE; - end - IBS_TIME_ERROR : - begin - error_code <= CODE_TIME_ERROR; - ibs_state <= IBS_ERROR_DONE; - end - IBS_SEQ_ERROR : - begin - error_code <= CODE_SEQ_ERROR; - ibs_state <= IBS_ERROR_DONE; - end + IBS_ERROR : + if(sample_fifo_src_rdy_i & eop) + ibs_state <= IBS_ERROR_DONE; + IBS_ERROR_DONE : ; endcase // case (ibs_state) - assign sample_fifo_dst_rdy_o = (ibs_state == IBS_UNDERRUN) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout + assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); assign error = (ibs_state == IBS_ERROR_DONE); -- cgit v1.2.3 From 9715fc389acfdb0d21b606f0f8c160ace4a4fa47 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 20 Jul 2010 17:29:45 -0700 Subject: more informative error codes --- usrp2/vrt/vita_tx_chain.v | 4 ++-- usrp2/vrt/vita_tx_control.v | 10 ++++++---- 2 files changed, 8 insertions(+), 6 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index ad9f11fc6..705be4a0e 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -25,10 +25,10 @@ module vita_tx_chain wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; wire error; - wire [3:0] error_code; + wire [15:0] error_code; assign underrun = error; - assign message = {28'h0,error_code}; + assign message = {16'h0,error_code}; setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index f45ba73f1..56a6c5a17 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -7,7 +7,7 @@ module vita_tx_control input [63:0] vita_time, output error, - output reg [3:0] error_code, + output reg [15:0] error_code, // From vita_tx_deframer input [5+64+WIDTH-1:0] sample_fifo_i, @@ -49,6 +49,8 @@ module vita_tx_control localparam CODE_UNDERRUN = 2; localparam CODE_SEQ_ERROR = 4; localparam CODE_TIME_ERROR = 8; + localparam CODE_UNDERRUN_MIDPKT = 16; + localparam CODE_SEQ_ERROR_MIDBURST = 32; reg [2:0] ibs_state; @@ -59,7 +61,7 @@ module vita_tx_control always @(posedge clk) if(reset | clear_state) - ibs_state <= 0; + ibs_state <= IBS_IDLE; else case(ibs_state) IBS_IDLE : @@ -82,7 +84,7 @@ module vita_tx_control if(~sample_fifo_src_rdy_i) begin ibs_state <= IBS_ERROR; - error_code <= CODE_UNDERRUN; + error_code <= CODE_UNDERRUN_MIDPKT; end else if(eop) if(eob) @@ -100,7 +102,7 @@ module vita_tx_control if(seqnum_err) begin ibs_state <= IBS_ERROR; - error_code <= CODE_SEQ_ERROR; + error_code <= CODE_SEQ_ERROR_MIDBURST; end else ibs_state <= IBS_RUN; -- cgit v1.2.3 From c5605beba381b13c3ceab7a5392a25ee8f336ca6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 21 Jul 2010 18:57:40 -0700 Subject: sequence errors can happen on start of burst as well. --- usrp2/vrt/vita_tx_deframer.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 55869b6e7..ce9f222e8 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -108,7 +108,7 @@ module vita_tx_deframer else vita_state <= VITA_PAYLOAD; seqnum_reg <= seqnum; - seqnum_err <= ~(is_sob | (seqnum == next_seqnum)); + seqnum_err <= ~(seqnum == next_seqnum); end // case: VITA_HEADER VITA_STREAMID : if(has_classid_reg) -- cgit v1.2.3 From 4a82c0640436e69081136cafc27194fd08ab6f1d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 27 Jul 2010 09:53:34 -0700 Subject: implemented "next packet" and "next burst" policies --- usrp2/vrt/vita_tx_chain.v | 6 ++--- usrp2/vrt/vita_tx_control.v | 61 +++++++++++++++++++++++++++++++------------- usrp2/vrt/vita_tx_deframer.v | 7 ++--- 3 files changed, 50 insertions(+), 24 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 705be4a0e..bcdbea820 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -14,7 +14,7 @@ module vita_tx_chain output [31:0] debug); localparam MAXCHAN = 1; - localparam FIFOWIDTH = 5+64+(32*MAXCHAN); + localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN); wire [FIFOWIDTH-1:0] tx1_data; wire tx1_src_rdy, tx1_dst_rdy; @@ -25,10 +25,10 @@ module vita_tx_chain wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; wire error; - wire [15:0] error_code; + wire [31:0] error_code; assign underrun = error; - assign message = {16'h0,error_code}; + assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 56a6c5a17..e02866af2 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -7,10 +7,10 @@ module vita_tx_control input [63:0] vita_time, output error, - output reg [15:0] error_code, + output reg [31:0] error_code, // From vita_tx_deframer - input [5+64+WIDTH-1:0] sample_fifo_i, + input [5+64+16+WIDTH-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, output sample_fifo_dst_rdy_o, @@ -22,14 +22,15 @@ module vita_tx_control output [31:0] debug ); - assign sample = sample_fifo_i[5+64+WIDTH-1:5+64]; + assign sample = sample_fifo_i[5+64+16+WIDTH-1:5+64+16]; wire [63:0] send_time = sample_fifo_i[63:0]; - wire eop = sample_fifo_i[64]; - wire eob = sample_fifo_i[65]; - wire sob = sample_fifo_i[66]; - wire send_at = sample_fifo_i[67]; - wire seqnum_err = sample_fifo_i[68]; + wire [15:0] seqnum = sample_fifo_i[79:64]; + wire eop = sample_fifo_i[80]; + wire eob = sample_fifo_i[81]; + wire sob = sample_fifo_i[82]; + wire send_at = sample_fifo_i[83]; + wire seqnum_err = sample_fifo_i[84]; wire now, early, late, too_early; @@ -46,11 +47,11 @@ module vita_tx_control localparam IBS_ERROR = 3; localparam IBS_ERROR_DONE = 4; - localparam CODE_UNDERRUN = 2; - localparam CODE_SEQ_ERROR = 4; - localparam CODE_TIME_ERROR = 8; - localparam CODE_UNDERRUN_MIDPKT = 16; - localparam CODE_SEQ_ERROR_MIDBURST = 32; + wire [31:0] CODE_UNDERRUN = {seqnum,16'd2}; + wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4}; + wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8}; + wire [31:0] CODE_UNDERRUN_MIDPKT = {seqnum,16'd16}; + wire [31:0] CODE_SEQ_ERROR_MIDBURST = {seqnum,16'd32}; reg [2:0] ibs_state; @@ -59,9 +60,22 @@ module vita_tx_control (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_state)); + wire [31:0] error_policy; + setting_reg #(.my_addr(BASE+3)) sr_error_policy + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(error_policy),.changed()); + + wire policy_wait = error_policy[0]; + wire policy_next_packet = error_policy[1]; + wire policy_next_burst = error_policy[2]; + reg send_error; + always @(posedge clk) if(reset | clear_state) - ibs_state <= IBS_IDLE; + begin + ibs_state <= IBS_IDLE; + send_error <= 0; + end else case(ibs_state) IBS_IDLE : @@ -70,6 +84,7 @@ module vita_tx_control begin ibs_state <= IBS_ERROR; error_code <= CODE_SEQ_ERROR; + send_error <= 1; end else if(~send_at | now) ibs_state <= IBS_RUN; @@ -77,6 +92,7 @@ module vita_tx_control begin ibs_state <= IBS_ERROR; error_code <= CODE_TIME_ERROR; + send_error <= 1; end IBS_RUN : @@ -85,6 +101,7 @@ module vita_tx_control begin ibs_state <= IBS_ERROR; error_code <= CODE_UNDERRUN_MIDPKT; + send_error <= 1; end else if(eop) if(eob) @@ -97,20 +114,27 @@ module vita_tx_control begin ibs_state <= IBS_ERROR_DONE; error_code <= CODE_UNDERRUN; + send_error <= 1; end else if(sample_fifo_src_rdy_i) if(seqnum_err) begin ibs_state <= IBS_ERROR; error_code <= CODE_SEQ_ERROR_MIDBURST; + send_error <= 1; end else ibs_state <= IBS_RUN; IBS_ERROR : - if(sample_fifo_src_rdy_i & eop) - ibs_state <= IBS_ERROR_DONE; - + begin + send_error <= 0; + if(sample_fifo_src_rdy_i & eop) + if(policy_next_packet | (policy_next_burst & eob)) + ibs_state <= IBS_IDLE; + else + ibs_state <= IBS_ERROR_DONE; + end IBS_ERROR_DONE : ; @@ -118,7 +142,8 @@ module vita_tx_control assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); - assign error = (ibs_state == IBS_ERROR_DONE); + //assign error = (ibs_state == IBS_ERROR_DONE); + assign error = send_error; assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index ce9f222e8..58878790d 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -10,7 +10,7 @@ module vita_tx_deframer input src_rdy_i, output dst_rdy_o, - output [5+64+(32*MAXCHAN)-1:0] sample_fifo_o, + output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o, output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, @@ -21,7 +21,7 @@ module vita_tx_deframer output [31:0] debug ); - localparam FIFOWIDTH = 5+64+(32*MAXCHAN); + localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN); wire [1:0] numchan; setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan @@ -185,7 +185,8 @@ module vita_tx_deframer .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) ); // sob, eob, has_secs (send_at) ignored on all lines except first - assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time}; + assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop, + 12'd0,seqnum_reg,send_time}; assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ; -- cgit v1.2.3 From e1591e4f6730f98d7e167d09f457f567edcdae81 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 28 Jul 2010 18:32:55 -0700 Subject: attempt at avoiding infinite error messages --- usrp2/vrt/vita_tx_control.v | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index e02866af2..35b6de4f0 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -46,6 +46,7 @@ module vita_tx_control localparam IBS_CONT_BURST = 2; localparam IBS_ERROR = 3; localparam IBS_ERROR_DONE = 4; + localparam IBS_ERROR_WAIT = 5; wire [31:0] CODE_UNDERRUN = {seqnum,16'd2}; wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4}; @@ -112,7 +113,12 @@ module vita_tx_control IBS_CONT_BURST : if(strobe) begin - ibs_state <= IBS_ERROR_DONE; + if(policy_next_packet) + ibs_state <= IBS_ERROR_DONE; + else if(policy_wait) + ibs_state <= IBS_ERROR_WAIT; + else + ibs_state <= IBS_ERROR; error_code <= CODE_UNDERRUN; send_error <= 1; end @@ -132,12 +138,15 @@ module vita_tx_control if(sample_fifo_src_rdy_i & eop) if(policy_next_packet | (policy_next_burst & eob)) ibs_state <= IBS_IDLE; - else - ibs_state <= IBS_ERROR_DONE; + else if(policy_wait) + ibs_state <= IBS_ERROR_WAIT; end - IBS_ERROR_DONE : - ; + IBS_ERROR_DONE : + send_error <= 0; + + IBS_ERROR_WAIT : + send_error <= 0; endcase // case (ibs_state) assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout -- cgit v1.2.3 From 41f9748a2d856aa3d1fe7b895e38ad3c4b65e11e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 28 Jul 2010 18:59:03 -0700 Subject: sequence number reset upon programming streamid --- usrp2/vrt/vita_tx_chain.v | 5 +++-- usrp2/vrt/vita_tx_deframer.v | 11 ++++++++--- 2 files changed, 11 insertions(+), 5 deletions(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index bcdbea820..662cdca62 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -26,16 +26,17 @@ module vita_tx_chain wire error; wire [31:0] error_code; + wire clear_seqnum; assign underrun = error; assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(streamid),.changed()); + .in(set_data),.out(streamid),.changed(clear_seqnum)); vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer - (.clk(clk), .reset(reset), .clear(clear_vita), + (.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 58878790d..f9cd7d00d 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -2,7 +2,7 @@ module vita_tx_deframer #(parameter BASE=0, parameter MAXCHAN=1) - (input clk, input reset, input clear, + (input clk, input reset, input clear, input clear_seqnum, input set_stb, input [7:0] set_addr, input [31:0] set_data, // To FIFO interface of Buffer Pool @@ -68,6 +68,13 @@ module vita_tx_deframer wire eop = eof | (pkt_len==hdr_len); // FIXME would ignoring eof allow larger VITA packets? wire fifo_space; + always @(posedge clk) + if(reset | clear_seqnum) + seqnum_reg <= 4'hF; + else + if((vita_state==VITA_HEADER) & src_rdy_i) + seqnum_reg <= seqnum; + always @(posedge clk) if(reset | clear) begin @@ -75,7 +82,6 @@ module vita_tx_deframer {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} <= 0; seqnum_err <= 0; - seqnum_reg <= 0; end else if((vita_state == VITA_STORE) & fifo_space) @@ -107,7 +113,6 @@ module vita_tx_deframer vita_state <= VITA_TICS; else vita_state <= VITA_PAYLOAD; - seqnum_reg <= seqnum; seqnum_err <= ~(seqnum == next_seqnum); end // case: VITA_HEADER VITA_STREAMID : -- cgit v1.2.3 From c174bf9acb2b2d142456f1186bd3e41e40d8a6d1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 29 Jul 2010 12:22:13 -0700 Subject: provide a way to get out of the error state without processor intervention --- usrp2/vrt/vita_tx_control.v | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 35b6de4f0..d0516bec8 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -143,7 +143,10 @@ module vita_tx_control end IBS_ERROR_DONE : - send_error <= 0; + begin + send_error <= 0; + ibs_state <= IBS_IDLE; + end IBS_ERROR_WAIT : send_error <= 0; -- cgit v1.2.3 From c4ae87f3554753877a35cab3b86cbf267fb2c035 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 11 Aug 2010 18:58:04 -0700 Subject: rx error context packets should not be marked as errors in the fifo --- usrp2/vrt/vita_rx_framer.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/vrt') diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v index fd82263d0..235817941 100644 --- a/usrp2/vrt/vita_rx_framer.v +++ b/usrp2/vrt/vita_rx_framer.v @@ -128,7 +128,7 @@ module vita_rx_framer VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]}; VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0}; VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]}; - VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b11,28'd0,flags_fifo_o}; + VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,28'd0,flags_fifo_o}; //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer}; default : pkt_fifo_line <= 34'h0_FFFF_FFFF; -- cgit v1.2.3