From e650ed086c68c9e3458c91817fd0b01da261cd57 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 11 Oct 2010 16:39:31 -0700 Subject: switch to 32 bit sequence numbers. Will wrap in ~15 hours at max rate --- usrp2/vrt/vita_tx_deframer.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'usrp2/vrt/vita_tx_deframer.v') diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index d8575b745..40867cc55 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -15,7 +15,7 @@ module vita_tx_deframer output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, - output [15:0] current_seqnum, + output [31:0] current_seqnum, // FIFO Levels output [15:0] fifo_occupied, @@ -48,9 +48,9 @@ module vita_tx_deframer reg [1:0] vector_phase; wire line_done; - wire [15:0] seqnum = data_i[15:0]; - reg [15:0] seqnum_reg; - wire [15:0] next_seqnum = seqnum_reg + 16'd1; + wire [31:0] seqnum = data_i; + reg [31:0] seqnum_reg; + wire [31:0] next_seqnum = seqnum_reg + 32'd1; wire [3:0] vita_seqnum = data_i[19:16]; reg [3:0] vita_seqnum_reg; wire [3:0] next_vita_seqnum = vita_seqnum_reg[3:0] + 4'd1; @@ -80,7 +80,7 @@ module vita_tx_deframer always @(posedge clk) if(reset | clear_seqnum) begin - seqnum_reg <= 16'hFFFF; + seqnum_reg <= 32'hFFFF_FFFF; vita_seqnum_reg <= 4'hF; end else -- cgit v1.2.3