From 8b377a9d6d0ad281474a8dbff49ea3b093178b28 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 22 Jan 2010 16:00:45 -0800 Subject: moved into subdir --- usrp2/vrt/vita_rx_framer.v | 199 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 usrp2/vrt/vita_rx_framer.v (limited to 'usrp2/vrt/vita_rx_framer.v') diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v new file mode 100644 index 000000000..d3ff98df7 --- /dev/null +++ b/usrp2/vrt/vita_rx_framer.v @@ -0,0 +1,199 @@ + +module vita_rx_framer + #(parameter BASE=0, + parameter MAXCHAN=1) + (input clk, input reset, input clear, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + // To FIFO interface of Buffer Pool + output [35:0] data_o, + input dst_rdy_i, + output src_rdy_o, + + // From vita_rx_control + input [4+64+(32*MAXCHAN)-1:0] sample_fifo_i, + input sample_fifo_src_rdy_i, + output sample_fifo_dst_rdy_o, + + // FIFO Levels + output [15:0] fifo_occupied, + output fifo_full, + output fifo_empty, + + output [31:0] debug_rx + ); + + localparam SAMP_WIDTH = 4+64+(32*MAXCHAN); + reg [3:0] sample_phase; + wire [3:0] numchan; + wire [3:0] flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-4]; + wire [63:0] vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-5:SAMP_WIDTH-68]; + + reg [31:0] data_fifo_o; + + // The tools won't synthesize properly without this kludge because of the variable + // parameter length + + wire [127:0] FIXED_WIDTH_KLUDGE = sample_fifo_i; + always @* + case(sample_phase) + 4'd0 : data_fifo_o = FIXED_WIDTH_KLUDGE[31:0]; + 4'd1 : data_fifo_o = FIXED_WIDTH_KLUDGE[63:32]; + 4'd2 : data_fifo_o = FIXED_WIDTH_KLUDGE[95:64]; + 4'd3 : data_fifo_o = FIXED_WIDTH_KLUDGE[127:96]; + default : data_fifo_o = 32'hDEADBEEF; + endcase // case (sample_phase) + + wire clear_pkt_count, pkt_fifo_rdy, sample_fifo_in_rdy; + + wire [31:0] vita_header, vita_streamid, vita_trailer; + wire [15:0] samples_per_packet; + + reg [33:0] pkt_fifo_line; + reg [3:0] vita_state; + reg [15:0] sample_ctr; + reg [3:0] pkt_count; + + wire [15:0] vita_pkt_len = samples_per_packet + 6; + //wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done}; + + wire clear_reg; + wire clear_int = clear | clear_reg; + + setting_reg #(.my_addr(BASE+3)) sr_clear + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_reg)); + + setting_reg #(.my_addr(BASE+4)) sr_header + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(vita_header),.changed()); + + setting_reg #(.my_addr(BASE+5)) sr_streamid + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(vita_streamid),.changed(clear_pkt_count)); + + setting_reg #(.my_addr(BASE+6)) sr_trailer + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(vita_trailer),.changed()); + + setting_reg #(.my_addr(BASE+7)) sr_samples_per_pkt + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(samples_per_packet),.changed()); + + setting_reg #(.my_addr(BASE+8), .at_reset(1)) sr_numchan + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(numchan),.changed()); + + // Output FIFO for packetized data + localparam VITA_IDLE = 0; + localparam VITA_HEADER = 1; + localparam VITA_STREAMID = 2; + localparam VITA_SECS = 3; + localparam VITA_TICS = 4; + localparam VITA_TICS2 = 5; + localparam VITA_PAYLOAD = 6; + localparam VITA_TRAILER = 7; + localparam VITA_ERR_HEADER = 9; // All ERR at 4'b1000 or'ed with base + localparam VITA_ERR_STREAMID = 10; + localparam VITA_ERR_SECS = 11; + localparam VITA_ERR_TICS = 12; + localparam VITA_ERR_TICS2 = 13; + localparam VITA_ERR_PAYLOAD = 14; + localparam VITA_ERR_TRAILER = 15; + + always @(posedge clk) + if(reset | clear_pkt_count) + pkt_count <= 0; + else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy) + pkt_count <= pkt_count + 1; + + always @* + case(vita_state) + VITA_HEADER, VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,vita_header[31:20],pkt_count,vita_pkt_len}; + VITA_STREAMID, VITA_ERR_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid}; + VITA_SECS, VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]}; + VITA_TICS, VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0}; + VITA_TICS2, VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]}; + VITA_PAYLOAD : pkt_fifo_line <= {2'b00,data_fifo_o}; + VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b00,28'd0,flags_fifo_o}; + VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer}; + VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer}; + default : pkt_fifo_line <= 34'h0_FFFF_FFFF; + endcase // case (vita_state) + + always @(posedge clk) + if(reset) + begin + vita_state <= VITA_IDLE; + sample_ctr <= 0; + sample_phase <= 0; + end + else + if(vita_state==VITA_IDLE) + begin + sample_ctr <= 1; + sample_phase <= 0; + if(sample_fifo_src_rdy_i) + if(|flags_fifo_o[3:1]) + vita_state <= VITA_ERR_HEADER; + else + vita_state <= VITA_HEADER; + end + else if(pkt_fifo_rdy) + case(vita_state) + VITA_PAYLOAD : + if(sample_fifo_src_rdy_i) + begin + if(sample_phase == (numchan-4'd1)) + begin + sample_phase <= 0; + sample_ctr <= sample_ctr + 1; + if(sample_ctr == samples_per_packet) + vita_state <= VITA_TRAILER; + if(|flags_fifo_o) // end early if any flag is set + vita_state <= VITA_TRAILER; + end + else + sample_phase <= sample_phase + 1; + end + VITA_TRAILER, VITA_ERR_TRAILER : + vita_state <= VITA_IDLE; + default : + vita_state <= vita_state + 1; + endcase // case (vita_state) + + reg req_write_pkt_fifo; + always @* + case(vita_state) + VITA_IDLE : + req_write_pkt_fifo <= 0; + VITA_HEADER, VITA_STREAMID, VITA_SECS, VITA_TICS, VITA_TICS2, VITA_TRAILER : + req_write_pkt_fifo <= 1; + VITA_PAYLOAD : + // Write if sample ready and no error flags + req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]); + VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD, VITA_ERR_TRAILER : + req_write_pkt_fifo <= 1; + default : + req_write_pkt_fifo <= 0; + endcase // case (vita_state) + + //wire req_write_pkt_fifo = (vita_state != VITA_IDLE) & (sample_fifo_src_rdy_i | (vita_state != VITA_PAYLOAD)); + + // Short FIFO to buffer between us and the FIFOs outside + fifo_short #(.WIDTH(34)) rx_pkt_fifo + (.clk(clk), .reset(reset), .clear(clear_int), + .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy), + .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), + .space(),.occupied(fifo_occupied[4:0]) ); + assign fifo_occupied[15:5] = 0; + assign data_o[35:34] = 2'b00; // Always write full lines + assign sample_fifo_dst_rdy_o = pkt_fifo_rdy & + ( ((vita_state==VITA_PAYLOAD) & + (sample_phase == (numchan-4'd1)) & + ~|flags_fifo_o[3:1]) | + (vita_state==VITA_ERR_TRAILER)); + + assign debug_rx = 0; + +endmodule // rx_control -- cgit v1.2.3 From c01b45d1db39db05998bc7914372209ae1017d0c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 10 Mar 2010 18:59:14 -0800 Subject: more debug for fixing E's --- usrp2/top/u2_core/u2_core.v | 17 ++++++++++++----- usrp2/vrt/vita_rx_framer.v | 2 +- 2 files changed, 13 insertions(+), 6 deletions(-) (limited to 'usrp2/vrt/vita_rx_framer.v') diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 9975f16a6..9a99ac536 100644 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -583,19 +583,25 @@ module u2_core .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), .debug(debug_rx_dsp) ); + wire [31:0] vrc_debug; + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(overrun), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy)); + .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), + .debug_rx(vrc_debug)); + wire [3:0] vita_state; + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty() ); + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vita_state) ); fifo_cascade #(.WIDTH(36), .SIZE(10)) rx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), @@ -743,9 +749,10 @@ module u2_core { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; */ - assign debug = debug_udp; - assign debug_gpio_0 = { {8'd0}, - {4'd0, rx_data[99:96]}, +// assign debug = debug_udp; + assign debug = vrc_debug; + assign debug_gpio_0 = { {4'd0, vita_state}, + {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}}; diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v index d3ff98df7..f3a81664a 100644 --- a/usrp2/vrt/vita_rx_framer.v +++ b/usrp2/vrt/vita_rx_framer.v @@ -194,6 +194,6 @@ module vita_rx_framer ~|flags_fifo_o[3:1]) | (vita_state==VITA_ERR_TRAILER)); - assign debug_rx = 0; + assign debug_rx = vita_state; endmodule // rx_control -- cgit v1.2.3