From a9d307124faa679df8180b5624e9250555306d67 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 4 Feb 2012 16:38:54 -0800 Subject: dsp rework: pass vita clears into dsp modules, unified fifo clears --- usrp2/vrt/vita_rx_chain.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'usrp2/vrt/vita_rx_chain.v') diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index e4f7e9864..c57e6cc05 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -28,9 +28,9 @@ module vita_rx_chain input [63:0] vita_time, input [31:0] sample, input strobe, output [35:0] rx_data_o, output rx_src_rdy_o, input rx_dst_rdy_i, - output overrun, output run, + output overrun, output run, output clear_o, output [31:0] debug ); - + wire [100:0] sample_data; wire sample_dst_rdy, sample_src_rdy; wire [31:0] vrc_debug, vrf_debug; @@ -39,6 +39,7 @@ module vita_rx_chain wire rx_src_rdy_int, rx_dst_rdy_int; wire clear; + assign clear_o = clear; setting_reg #(.my_addr(BASE+3)) sr (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), -- cgit v1.2.3