From 587dfe7db4b4749ffedb5e7e3a0a36a83dd90c6a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 7 Nov 2010 11:51:28 -0800 Subject: clear out the vita tx chain and the tx fifo. need to check the fifo reset to make sure it is in the correct clock domain. --- usrp2/vrt/gen_context_pkt.v | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'usrp2/vrt/gen_context_pkt.v') diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 0eb035f3e..efc170743 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -38,9 +38,10 @@ module gen_context_pkt stored_message <= message; else if(ctxt_state == CTXT_FLOWCTRL1) stored_message <= 0; - + + // Don't want to clear most of this to avoid getting stuck with a half packet in the pipe always @(posedge clk) - if(reset | clear) + if(reset) begin ctxt_state <= CTXT_IDLE; seqno <= 0; @@ -84,7 +85,7 @@ module gen_context_pkt endcase // case (ctxt_state) fifo_short #(.WIDTH(34)) ctxt_fifo - (.clk(clk), .reset(reset), .clear(clear), + (.clk(clk), .reset(reset), .clear(0), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); assign data_o[35:34] = 2'b00; -- cgit v1.2.3