From a8ceedc34bb66c870964e4430c098a2cdaf9d429 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 25 Jan 2010 12:45:23 -0800 Subject: just debug pin changes --- usrp2/udp/udp_wrapper.v | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'usrp2/udp') diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v index 5a78cd09c..390abd0d5 100644 --- a/usrp2/udp/udp_wrapper.v +++ b/usrp2/udp/udp_wrapper.v @@ -77,9 +77,16 @@ module udp_wrapper .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i), .space(), .occupied() ); + /* assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, { rx_int3_data[35:32], rx_f36_data[35:32] }, { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } }; + */ + + assign debug = { { 3'd0, tx_int1_src_rdy, tx_int1_dst_rdy, tx_int1_data[18:16] }, + { 3'd0, tx_int2_src_rdy, tx_int2_dst_rdy, tx_int2_data[18:16] }, + { tx_int2_data[15:8] }, + { tx_int2_data[7:0] } }; endmodule // udp_wrapper -- cgit v1.2.3