From 8b377a9d6d0ad281474a8dbff49ea3b093178b28 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 22 Jan 2010 16:00:45 -0800 Subject: moved into subdir --- usrp2/udp/add_onescomp.v | 12 ++++ usrp2/udp/fifo19_rxrealign.v | 42 +++++++++++ usrp2/udp/prot_eng_rx.v | 121 +++++++++++++++++++++++++++++++ usrp2/udp/prot_eng_tx.v | 119 ++++++++++++++++++++++++++++++ usrp2/udp/prot_eng_tx_tb.v | 167 +++++++++++++++++++++++++++++++++++++++++++ usrp2/udp/udp_wrapper.v | 85 ++++++++++++++++++++++ 6 files changed, 546 insertions(+) create mode 100644 usrp2/udp/add_onescomp.v create mode 100644 usrp2/udp/fifo19_rxrealign.v create mode 100644 usrp2/udp/prot_eng_rx.v create mode 100644 usrp2/udp/prot_eng_tx.v create mode 100644 usrp2/udp/prot_eng_tx_tb.v create mode 100644 usrp2/udp/udp_wrapper.v (limited to 'usrp2/udp') diff --git a/usrp2/udp/add_onescomp.v b/usrp2/udp/add_onescomp.v new file mode 100644 index 000000000..048842a86 --- /dev/null +++ b/usrp2/udp/add_onescomp.v @@ -0,0 +1,12 @@ + + +module add_onescomp + #(parameter WIDTH = 16) + (input [WIDTH-1:0] A, + input [WIDTH-1:0] B, + output [WIDTH-1:0] SUM); + + wire [WIDTH:0] SUM_INT = {1'b0,A} + {1'b0,B}; + assign SUM = SUM_INT[WIDTH-1:0] + {{WIDTH-1{1'b0}},SUM_INT[WIDTH]}; + +endmodule // add_onescomp diff --git a/usrp2/udp/fifo19_rxrealign.v b/usrp2/udp/fifo19_rxrealign.v new file mode 100644 index 000000000..35ad90951 --- /dev/null +++ b/usrp2/udp/fifo19_rxrealign.v @@ -0,0 +1,42 @@ + + +// Adds a junk line at the beginning of every packet, which the +// following stages should ignore. This gives us proper alignment due +// to the 14 byte ethernet header + +// Bit 18 -- odd length +// Bit 17 -- eof +// Bit 16 -- sof +// Bit 15:0 -- data + +module fifo19_rxrealign + (input clk, input reset, input clear, + input [18:0] datain, input src_rdy_i, output dst_rdy_o, + output [18:0] dataout, output src_rdy_o, input dst_rdy_i); + + reg rxre_state; + localparam RXRE_DUMMY = 0; + localparam RXRE_PKT = 1; + + assign dataout[18] = datain[18]; + assign dataout[17] = datain[17]; + assign dataout[16] = (rxre_state==RXRE_DUMMY) | (datain[17] & datain[16]); // allows for passing error signal + assign dataout[15:0] = datain[15:0]; + + always @(posedge clk) + if(reset | clear) + rxre_state <= RXRE_DUMMY; + else if(src_rdy_i & dst_rdy_i) + case(rxre_state) + RXRE_DUMMY : + rxre_state <= RXRE_PKT; + RXRE_PKT : + if(datain[17]) // if eof or error + rxre_state <= RXRE_DUMMY; + endcase // case (rxre_state) + + assign src_rdy_o = src_rdy_i & dst_rdy_i; // Send anytime both sides are ready + assign dst_rdy_o = src_rdy_i & dst_rdy_i & (rxre_state == RXRE_PKT); // Only consume after the dummy + +endmodule // fifo19_rxrealign + diff --git a/usrp2/udp/prot_eng_rx.v b/usrp2/udp/prot_eng_rx.v new file mode 100644 index 000000000..5df158b2b --- /dev/null +++ b/usrp2/udp/prot_eng_rx.v @@ -0,0 +1,121 @@ + + + +// Protocol Engine Receiver +// Checks each line (16 bits) against values in setting regs +// 3 options for each line -- +// Error if mismatch, Slowpath if mismatch, or ignore line +// The engine increases the length of each packet by 32 or 48 bits, +// bringing the total length to a multiple of 32 bits. The last line +// is entirely new, and contains the results of the matching operation: +// 16 bits of flags, 16 bits of data. Flags indicate error or slowpath +// Data indicates line that caused mismatch if any. + + +// Flags[2:0] is {occ, eop, sop} +// Protocol word format is: +// 22 Last Header Line +// 21 SLOWPATH if mismatch +// 20 ERROR if mismatch +// 19 This is the IP checksum +// 18 This is the UDP checksum +// 17 Compute IP checksum on this word +// 16 Compute UDP checksum on this word +// 15:0 data word to be matched + +module prot_eng_rx + #(parameter BASE=0) + (input clk, input reset, input clear, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input [18:0] datain, input src_rdy_i, output dst_rdy_o, + output [18:0] dataout, output src_rdy_o, input dst_rdy_i); + + localparam HDR_WIDTH = 16 + 7; // 16 bits plus flags + localparam HDR_LEN = 32; // Up to 64 bytes of protocol + + // Store header values in a small dual-port (distributed) ram + reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1]; + wire [HDR_WIDTH-1:0] header_word; + + always @(posedge clk) + if(set_stb & ((set_addr & 8'hE0) == BASE)) + header_ram[set_addr[4:0]] <= set_data; + + assign header_word = header_ram[state]; + + wire consume_input = src_rdy_i & dst_rdy_o; + wire produce_output = src_rdy_o & dst_rdy_i; + + // Main State Machine + reg [15:0] pkt_length, fail_word, dataout_int; + + reg slowpath, error, sof_o, eof_o, occ_o, odd; + + assign dataout = {occ_o, eof_o, sof_o, dataout_int}; + + wire [15:0] calc_ip_checksum, calc_udp_checksum; + reg [15:0] rx_ip_checksum, rx_udp_checksum; + + always @(posedge clk) + if(header_word[19]) + rx_ip_checksum <= datain[15:0]; + always @(posedge clk) + if(header_word[18]) + rx_udp_checksum <= datain[15:0]; + + always @(posedge clk) + if(reset | clear) + begin + slowpath <= 0; + error <= 0; + state <= 0; + fail_word <= 0; + eof_o <= 0; + occ_o <= 0; + end + else if(src_rdy_i & dst_rdy_i) + case (state) + 0 : + begin + slowpath <= 0; + error <= 0; + eof_o <= 0; + occ_o <= 0; + state <= 1; + end + + ST_SLOWPATH : + ; + ST_ERROR : + ; + ST_PAYLOAD : + ; + ST_FILLER : + ; + ST_END1 : + ; + ST_END2 : + ; + default : + if(header_word[21] && mismatch) + state <= ST_SLOWPATH; + else if(header_word[20] && mismatch) + state <= ST_ERROR; + else if(header_word[22]) + state <= ST_PAYLOAD; + else + state <= state + 1; + endcase // case (state) + + + + // IP + UDP checksum state machines + checksum_sm ip_chk + (.clk(clk), .reset(reset), .in(datain), + .calc(consume_input & header_word[17]), .clear(state==0), .checksum(ip_checksum)); + + checksum_sm udp_chk + (.clk(clk), .reset(reset), .in(datain), + .calc(consume_input & header_word[16]), .clear(state==0), .checksum(udp_checksum)); + +endmodule // prot_eng_rx diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v new file mode 100644 index 000000000..9031011f7 --- /dev/null +++ b/usrp2/udp/prot_eng_tx.v @@ -0,0 +1,119 @@ + +// The input FIFO contents should be 16 bits wide +// The first word is 1 for fast path (accelerated protocol) +// 0 for software implemented protocol +// The second word is the number of bytes in the packet, +// and must be valid even if we are in slow path mode +// Odd means the last word is half full +// Flags[1:0] is {eop, sop} +// Protocol word format is: +// 19 Last Header Line +// 18 IP Header Checksum XOR +// 17 IP Length Here +// 16 UDP Length Here +// 15:0 data word to be sent + +module prot_eng_tx + #(parameter BASE=0) + (input clk, input reset, input clear, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input [18:0] datain, input src_rdy_i, output dst_rdy_o, + output [18:0] dataout, output src_rdy_o, input dst_rdy_i); + + wire [2:0] flags_i = datain[18:16]; + reg [15:0] dataout_int; + reg fast_path, sof_o; + + wire [2:0] flags_o = {flags_i[2], flags_i[1], sof_o}; // OCC, EOF, SOF + + assign dataout = {flags_o[2:0], dataout_int[15:0]}; + + reg [4:0] state; + wire do_payload = (state == 31); + + assign dst_rdy_o = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30)); + assign src_rdy_o = src_rdy_i & ~((state==0) | (state==1) | (state==30)); + + localparam HDR_WIDTH = 16 + 4; // 16 bits plus flags + localparam HDR_LEN = 32; // Up to 64 bytes of protocol + + // Store header values in a small dual-port (distributed) ram + reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1]; + wire [HDR_WIDTH-1:0] header_word; + + always @(posedge clk) + if(set_stb & ((set_addr & 8'hE0) == BASE)) + header_ram[set_addr[4:0]] <= set_data; + + assign header_word = header_ram[state]; + + wire last_hdr_line = header_word[19]; + wire ip_chk = header_word[18]; + wire ip_len = header_word[17]; + wire udp_len = header_word[16]; + + // Protocol State Machine + reg [15:0] length; + wire [15:0] ip_length = length + 28; // IP HDR + UDP HDR + wire [15:0] udp_length = length + 8; // UDP HDR + + always @(posedge clk) + if(reset) + begin + state <= 0; + fast_path <= 0; + sof_o <= 0; + end + else + if(src_rdy_i & dst_rdy_i) + case(state) + 0 : + begin + fast_path <= datain[0]; + state <= 1; + end + 1 : + begin + length <= datain[15:0]; + sof_o <= 1; + if(fast_path) + state <= 2; + else + state <= 30; // Skip 1 word for alignment + end + 30 : + state <= 31; + 31 : + begin + sof_o <= 0; + if(flags_i[1]) // eop + state <= 0; + end + default : + begin + sof_o <= 0; + if(~last_hdr_line) + state <= state + 1; + else + state <= 31; + end + endcase // case (state) + + wire [15:0] checksum; + add_onescomp #(.WIDTH(16)) add_onescomp + (.A(header_word[15:0]),.B(ip_length),.SUM(checksum)); + + always @* + if(ip_chk) + //dataout_int <= header_word[15:0] ^ ip_length; + dataout_int <= 16'hFFFF ^ checksum; + else if(ip_len) + dataout_int <= ip_length; + else if(udp_len) + dataout_int <= udp_length; + else if(do_payload) + dataout_int <= datain[15:0]; + else + dataout_int <= header_word[15:0]; + +endmodule // prot_eng_tx diff --git a/usrp2/udp/prot_eng_tx_tb.v b/usrp2/udp/prot_eng_tx_tb.v new file mode 100644 index 000000000..e7ffeb5e1 --- /dev/null +++ b/usrp2/udp/prot_eng_tx_tb.v @@ -0,0 +1,167 @@ +module prot_eng_tx_tb(); + + localparam BASE = 128; + reg clk = 0; + reg rst = 1; + reg clear = 0; + initial #1000 rst = 0; + always #50 clk = ~clk; + + reg [31:0] f36_data; + reg [1:0] f36_occ; + reg f36_sof, f36_eof; + + wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data}; + reg src_rdy_f36i = 0; + reg [15:0] count; + + wire [35:0] casc_do; + wire [18:0] final_out, prot_out; + + wire src_rdy_final, dst_rdy_final, src_rdy_prot; + reg dst_rdy_prot =0; + + wire dst_rdy_f36o ; + fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36 + (.clk(clk),.reset(rst),.clear(clear), + .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), + .dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o)); + + fifo36_to_fifo19 fifo_converter + (.clk(clk),.reset(rst),.clear(clear), + .f36_datain(casc_do),.f36_src_rdy_i(src_rdy_f36o),.f36_dst_rdy_o(dst_rdy_f36o), + .f19_dataout(final_out),.f19_src_rdy_o(src_rdy_final),.f19_dst_rdy_i(dst_rdy_final)); + + reg set_stb; + reg [7:0] set_addr; + reg [31:0] set_data; + + prot_eng_tx #(.BASE(BASE)) prot_eng_tx + (.clk(clk), .reset(rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .datain(final_out[18:0]),.src_rdy_i(src_rdy_final),.dst_rdy_o(dst_rdy_final), + .dataout(prot_out[18:0]),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot)); + + reg [35:0] printer; + + task WriteSREG; + input [7:0] addr; + input [31:0] data; + + begin + @(posedge clk); + set_addr <= addr; + set_data <= data; + set_stb <= 1; + @(posedge clk); + set_stb <= 0; + end + endtask // WriteSREG + + task ReadFromFIFO36; + begin + $display("Read from FIFO36"); + #1 dst_rdy_prot <= 1; + while(~src_rdy_prot) + @(posedge clk); + while(1) + begin + while(~src_rdy_prot) + @(posedge clk); + $display("Read: %h",prot_out); + @(posedge clk); + end + end + endtask // ReadFromFIFO36 + + task PutPacketInFIFO36; + input [31:0] data_start; + input [31:0] data_len; + begin + count <= 4; + src_rdy_f36i <= 1; + f36_data <= 32'h0001_000c; + f36_sof <= 1; + f36_eof <= 0; + f36_occ <= 0; + + $display("Put Packet in FIFO36"); + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + $display("PPI_FIFO36: Entered First Line"); + f36_sof <= 0; + f36_data <= data_start; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + while(count+4 < data_len) + begin + f36_data <= f36_data + 32'h01010101; + count <= count + 4; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + $display("PPI_FIFO36: Entered New Line"); + end + f36_data <= f36_data + 32'h01010101; + f36_eof <= 1; + if(count + 4 == data_len) + f36_occ <= 0; + else if(count + 3 == data_len) + f36_occ <= 3; + else if(count + 2 == data_len) + f36_occ <= 2; + else + f36_occ <= 1; + while(~dst_rdy_f36i) + @(posedge clk); + @(posedge clk); + f36_occ <= 0; + f36_eof <= 0; + f36_data <= 0; + src_rdy_f36i <= 0; + $display("PPI_FIFO36: Entered Last Line"); + end + endtask // PutPacketInFIFO36 + + initial $dumpfile("prot_eng_tx_tb.vcd"); + initial $dumpvars(0,prot_eng_tx_tb); + + initial + begin + #10000; + @(posedge clk); + ReadFromFIFO36; + end + + initial + begin + @(negedge rst); + @(posedge clk); + WriteSREG(BASE, {12'b0, 4'h0, 16'h0000}); + WriteSREG(BASE+1, {12'b0, 4'h0, 16'h0000}); + WriteSREG(BASE+2, {12'b0, 4'h0, 16'hABCD}); + WriteSREG(BASE+3, {12'b0, 4'h0, 16'h1234}); + WriteSREG(BASE+4, {12'b0, 4'h8, 16'h5678}); + WriteSREG(BASE+5, {12'b0, 4'h0, 16'hABCD}); + WriteSREG(BASE+6, {12'b0, 4'h0, 16'hABCD}); + WriteSREG(BASE+7, {12'b0, 4'h0, 16'hABCD}); + WriteSREG(BASE+8, {12'b0, 4'h0, 16'hABCD}); + WriteSREG(BASE+9, {12'b0, 4'h0, 16'hABCD}); + @(posedge clk); + PutPacketInFIFO36(32'hA0B0C0D0,16); + @(posedge clk); + @(posedge clk); + #10000; + @(posedge clk); + PutPacketInFIFO36(32'hE0F0A0B0,36); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + + initial #20000 $finish; +endmodule // prot_eng_tx_tb diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v new file mode 100644 index 000000000..6e8d19dfd --- /dev/null +++ b/usrp2/udp/udp_wrapper.v @@ -0,0 +1,85 @@ + +module udp_wrapper + #(parameter BASE=0, + parameter RXFIFOSIZE=11) + (input clk, input reset, input clear, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o, + output [18:0] tx_f19_data, output tx_f19_src_rdy_o, input tx_f19_dst_rdy_i, + + output [35:0] rx_f36_data, output rx_f36_src_rdy_o, input rx_f36_dst_rdy_i, + input [35:0] tx_f36_data, input tx_f36_src_rdy_i, output tx_f36_dst_rdy_o, + output [31:0] debug + ); + + wire tx_int1_src_rdy, tx_int1_dst_rdy; + wire [18:0] tx_int1_data; + + wire tx_int2_src_rdy, tx_int2_dst_rdy; + wire [18:0] tx_int2_data; + wire [31:0] debug_state; + + // TX side + fifo36_to_fifo19 fifo36_to_fifo19 + (.clk(clk), .reset(reset), .clear(clear), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_), .f36_dst_rdy_o(tx_f36_dst_rdy_o), + .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) ); + + fifo_short #(.WIDTH(19)) shortfifo19_a + (.clk(clk), .reset(reset), .clear(clear), + .datain(tx_int1_data), .src_rdy_i(tx_int1_src_rdy), .dst_rdy_o(tx_int1_dst_rdy), + .dataout(tx_int2_data), .src_rdy_o(tx_int2_src_rdy), .dst_rdy_i(tx_int2_dst_rdy), + .space(), .occupied() ); + + prot_eng_tx #(.BASE(BASE)) prot_eng_tx + (.clk(clk), .reset(reset), .clear(clear), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .datain(tx_int2_data), .src_rdy_i(tx_int2_src_rdy), .dst_rdy_o(tx_int2_dst_rdy), + .dataout(tx_f19_data), .src_rdy_o(tx_f19_src_rdy_o), .dst_rdy_i(tx_f19_dst_rdy_i) ); + + // RX side + wire rx_int1_src_rdy, rx_int1_dst_rdy; + wire [18:0] rx_int1_data; + + wire rx_int2_src_rdy, rx_int2_dst_rdy; + wire [18:0] rx_int2_data; + + wire rx_int3_src_rdy, rx_int3_dst_rdy; + wire [35:0] rx_int3_data; + +`ifdef USE_PROT_ENG + prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx + (.clk(clk), .reset(reset), .clear(clear), + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o), + .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) ); +`else + fifo19_rxrealign fifo19_rxrealign + (.clk(clk), .reset(reset), .clear(clear), + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o), + .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) ); +`endif // !`ifdef USE_PROT_ENG + + fifo_short #(.WIDTH(19)) shortfifo19_b + (.clk(clk), .reset(reset), .clear(clear), + .datain(rx_int1_data), .src_rdy_i(rx_int1_src_rdy), .dst_rdy_o(rx_int1_dst_rdy), + .dataout(rx_int2_data), .src_rdy_o(rx_int2_src_rdy), .dst_rdy_i(rx_int2_dst_rdy), + .space(), .occupied() ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk), .reset(reset), .clear(clear), + .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy), + .f36_dataout(rx_int3_data), .f36_src_rdy_o(rx_int3_src_rdy), .f36_dst_rdy_i(rx_int3_dst_rdy), + .debug(debug_state)); + + fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy), + .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i), + .space(), .occupied() ); + + assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, + { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, + { rx_int3_data[35:32], rx_f36_data[35:32] }, + { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } }; + +endmodule // udp_wrapper -- cgit v1.2.3 From ab2f3f78bb3f6b88190312b06a6476c3a08561d2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 23 Jan 2010 01:05:13 -0800 Subject: typo caused the tx udp chain to be disconnected --- usrp2/udp/udp_wrapper.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/udp') diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v index 6e8d19dfd..5a78cd09c 100644 --- a/usrp2/udp/udp_wrapper.v +++ b/usrp2/udp/udp_wrapper.v @@ -22,7 +22,7 @@ module udp_wrapper // TX side fifo36_to_fifo19 fifo36_to_fifo19 (.clk(clk), .reset(reset), .clear(clear), - .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_), .f36_dst_rdy_o(tx_f36_dst_rdy_o), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_i), .f36_dst_rdy_o(tx_f36_dst_rdy_o), .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) ); fifo_short #(.WIDTH(19)) shortfifo19_a -- cgit v1.2.3 From a8ceedc34bb66c870964e4430c098a2cdaf9d429 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 25 Jan 2010 12:45:23 -0800 Subject: just debug pin changes --- usrp2/top/u2_core/u2_core.v | 6 +++++- usrp2/udp/udp_wrapper.v | 7 +++++++ 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'usrp2/udp') diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index f5cc55670..78ddd515c 100644 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -745,7 +745,11 @@ module u2_core assign debug = debug_udp; assign debug_gpio_0 = debug_mac; - assign debug_gpio_1 = { rx_f19_src_rdy, rx_f19_dst_rdy, rx_f19_data }; + assign debug_gpio_1 = { { tx_f19_data[15:8] }, + { tx_f19_data[7:0] }, + { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, + { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; + endmodule // u2_core diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v index 5a78cd09c..390abd0d5 100644 --- a/usrp2/udp/udp_wrapper.v +++ b/usrp2/udp/udp_wrapper.v @@ -77,9 +77,16 @@ module udp_wrapper .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i), .space(), .occupied() ); + /* assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, { rx_int3_data[35:32], rx_f36_data[35:32] }, { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } }; + */ + + assign debug = { { 3'd0, tx_int1_src_rdy, tx_int1_dst_rdy, tx_int1_data[18:16] }, + { 3'd0, tx_int2_src_rdy, tx_int2_dst_rdy, tx_int2_data[18:16] }, + { tx_int2_data[15:8] }, + { tx_int2_data[7:0] } }; endmodule // udp_wrapper -- cgit v1.2.3 From fdb6175aef0aa1896c6319d5425955ce0a5dc86b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Mar 2010 14:00:37 -0700 Subject: moved fifos around, now easier to see where they are and how big --- usrp2/top/u2_core/u2_core.v | 33 +++++++++++++++++++++++---------- usrp2/udp/udp_wrapper.v | 14 +++++++------- 2 files changed, 30 insertions(+), 17 deletions(-) (limited to 'usrp2/udp') diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 44715a04f..cd0199005 100644 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -144,6 +144,15 @@ module u2_core localparam SR_SIMTIMER = 198; // 2 localparam SR_TX_DSP = 208; // 16 localparam SR_TX_CTRL = 224; // 16 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + localparam DSP_TX_FIFOSIZE = 10; + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 10; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? wire [7:0] set_addr; wire [31:0] set_data; @@ -440,24 +449,28 @@ module u2_core .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] buffer_udp; - wire udp_src_rdy, udp_dst_rdy; + wire [35:0] udp_tx_data, udp_rx_data; + wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), - .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy_o(wr2_ready_i), .rx_f36_dst_rdy_i(wr2_ready_o), -// .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy_i(rd2_ready_o), .tx_f36_dst_rdy_o(rd2_ready_i), - .tx_f36_data(buffer_udp), .tx_f36_src_rdy_i(udp_src_rdy), .tx_f36_dst_rdy_o(udp_dst_rdy), + .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), + .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), .debug(debug_udp) ); - fifo_cascade #(.WIDTH(36), .SIZE(10)) txudp_fifo_cascade + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(buffer_udp), .src_rdy_o(udp_src_rdy), .dst_rdy_i(udp_dst_rdy)); + .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus @@ -612,7 +625,7 @@ module u2_core .fifo_occupied(), .fifo_full(), .fifo_empty(), .debug_rx(vita_state) ); - fifo_cascade #(.WIDTH(36), .SIZE(10)) rx_fifo_cascade + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); @@ -626,7 +639,7 @@ module u2_core wire [31:0] debug_vtc, debug_vtd, debug_vt; - fifo_cascade #(.WIDTH(36), .SIZE(10)) tx_fifo_cascade + fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); @@ -660,7 +673,7 @@ module u2_core // /////////////////////////////////////////////////////////////////////////////////// // SERDES - serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes (.clk(dsp_clk),.rst(dsp_rst), .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v index 390abd0d5..f4c642615 100644 --- a/usrp2/udp/udp_wrapper.v +++ b/usrp2/udp/udp_wrapper.v @@ -1,7 +1,6 @@ module udp_wrapper - #(parameter BASE=0, - parameter RXFIFOSIZE=11) + #(parameter BASE=0) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o, @@ -44,8 +43,8 @@ module udp_wrapper wire rx_int2_src_rdy, rx_int2_dst_rdy; wire [18:0] rx_int2_data; - wire rx_int3_src_rdy, rx_int3_dst_rdy; - wire [35:0] rx_int3_data; + //wire rx_int3_src_rdy, rx_int3_dst_rdy; + //wire [35:0] rx_int3_data; `ifdef USE_PROT_ENG prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx @@ -68,15 +67,16 @@ module udp_wrapper fifo19_to_fifo36 fifo19_to_fifo36 (.clk(clk), .reset(reset), .clear(clear), .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy), - .f36_dataout(rx_int3_data), .f36_src_rdy_o(rx_int3_src_rdy), .f36_dst_rdy_i(rx_int3_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy_o), .f36_dst_rdy_i(rx_f36_dst_rdy_i), .debug(debug_state)); - + + /* fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo (.clk(clk), .reset(reset), .clear(clear), .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy), .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i), .space(), .occupied() ); - +*/ /* assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, -- cgit v1.2.3