From 8b377a9d6d0ad281474a8dbff49ea3b093178b28 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 22 Jan 2010 16:00:45 -0800 Subject: moved into subdir --- usrp2/udp/udp_wrapper.v | 85 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 usrp2/udp/udp_wrapper.v (limited to 'usrp2/udp/udp_wrapper.v') diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v new file mode 100644 index 000000000..6e8d19dfd --- /dev/null +++ b/usrp2/udp/udp_wrapper.v @@ -0,0 +1,85 @@ + +module udp_wrapper + #(parameter BASE=0, + parameter RXFIFOSIZE=11) + (input clk, input reset, input clear, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o, + output [18:0] tx_f19_data, output tx_f19_src_rdy_o, input tx_f19_dst_rdy_i, + + output [35:0] rx_f36_data, output rx_f36_src_rdy_o, input rx_f36_dst_rdy_i, + input [35:0] tx_f36_data, input tx_f36_src_rdy_i, output tx_f36_dst_rdy_o, + output [31:0] debug + ); + + wire tx_int1_src_rdy, tx_int1_dst_rdy; + wire [18:0] tx_int1_data; + + wire tx_int2_src_rdy, tx_int2_dst_rdy; + wire [18:0] tx_int2_data; + wire [31:0] debug_state; + + // TX side + fifo36_to_fifo19 fifo36_to_fifo19 + (.clk(clk), .reset(reset), .clear(clear), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_), .f36_dst_rdy_o(tx_f36_dst_rdy_o), + .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) ); + + fifo_short #(.WIDTH(19)) shortfifo19_a + (.clk(clk), .reset(reset), .clear(clear), + .datain(tx_int1_data), .src_rdy_i(tx_int1_src_rdy), .dst_rdy_o(tx_int1_dst_rdy), + .dataout(tx_int2_data), .src_rdy_o(tx_int2_src_rdy), .dst_rdy_i(tx_int2_dst_rdy), + .space(), .occupied() ); + + prot_eng_tx #(.BASE(BASE)) prot_eng_tx + (.clk(clk), .reset(reset), .clear(clear), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .datain(tx_int2_data), .src_rdy_i(tx_int2_src_rdy), .dst_rdy_o(tx_int2_dst_rdy), + .dataout(tx_f19_data), .src_rdy_o(tx_f19_src_rdy_o), .dst_rdy_i(tx_f19_dst_rdy_i) ); + + // RX side + wire rx_int1_src_rdy, rx_int1_dst_rdy; + wire [18:0] rx_int1_data; + + wire rx_int2_src_rdy, rx_int2_dst_rdy; + wire [18:0] rx_int2_data; + + wire rx_int3_src_rdy, rx_int3_dst_rdy; + wire [35:0] rx_int3_data; + +`ifdef USE_PROT_ENG + prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx + (.clk(clk), .reset(reset), .clear(clear), + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o), + .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) ); +`else + fifo19_rxrealign fifo19_rxrealign + (.clk(clk), .reset(reset), .clear(clear), + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o), + .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) ); +`endif // !`ifdef USE_PROT_ENG + + fifo_short #(.WIDTH(19)) shortfifo19_b + (.clk(clk), .reset(reset), .clear(clear), + .datain(rx_int1_data), .src_rdy_i(rx_int1_src_rdy), .dst_rdy_o(rx_int1_dst_rdy), + .dataout(rx_int2_data), .src_rdy_o(rx_int2_src_rdy), .dst_rdy_i(rx_int2_dst_rdy), + .space(), .occupied() ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk), .reset(reset), .clear(clear), + .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy), + .f36_dataout(rx_int3_data), .f36_src_rdy_o(rx_int3_src_rdy), .f36_dst_rdy_i(rx_int3_dst_rdy), + .debug(debug_state)); + + fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy), + .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i), + .space(), .occupied() ); + + assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, + { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, + { rx_int3_data[35:32], rx_f36_data[35:32] }, + { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } }; + +endmodule // udp_wrapper -- cgit v1.2.3 From ab2f3f78bb3f6b88190312b06a6476c3a08561d2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 23 Jan 2010 01:05:13 -0800 Subject: typo caused the tx udp chain to be disconnected --- usrp2/udp/udp_wrapper.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/udp/udp_wrapper.v') diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v index 6e8d19dfd..5a78cd09c 100644 --- a/usrp2/udp/udp_wrapper.v +++ b/usrp2/udp/udp_wrapper.v @@ -22,7 +22,7 @@ module udp_wrapper // TX side fifo36_to_fifo19 fifo36_to_fifo19 (.clk(clk), .reset(reset), .clear(clear), - .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_), .f36_dst_rdy_o(tx_f36_dst_rdy_o), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_i), .f36_dst_rdy_o(tx_f36_dst_rdy_o), .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) ); fifo_short #(.WIDTH(19)) shortfifo19_a -- cgit v1.2.3 From a8ceedc34bb66c870964e4430c098a2cdaf9d429 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 25 Jan 2010 12:45:23 -0800 Subject: just debug pin changes --- usrp2/top/u2_core/u2_core.v | 6 +++++- usrp2/udp/udp_wrapper.v | 7 +++++++ 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'usrp2/udp/udp_wrapper.v') diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index f5cc55670..78ddd515c 100644 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -745,7 +745,11 @@ module u2_core assign debug = debug_udp; assign debug_gpio_0 = debug_mac; - assign debug_gpio_1 = { rx_f19_src_rdy, rx_f19_dst_rdy, rx_f19_data }; + assign debug_gpio_1 = { { tx_f19_data[15:8] }, + { tx_f19_data[7:0] }, + { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, + { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; + endmodule // u2_core diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v index 5a78cd09c..390abd0d5 100644 --- a/usrp2/udp/udp_wrapper.v +++ b/usrp2/udp/udp_wrapper.v @@ -77,9 +77,16 @@ module udp_wrapper .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i), .space(), .occupied() ); + /* assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, { rx_int3_data[35:32], rx_f36_data[35:32] }, { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } }; + */ + + assign debug = { { 3'd0, tx_int1_src_rdy, tx_int1_dst_rdy, tx_int1_data[18:16] }, + { 3'd0, tx_int2_src_rdy, tx_int2_dst_rdy, tx_int2_data[18:16] }, + { tx_int2_data[15:8] }, + { tx_int2_data[7:0] } }; endmodule // udp_wrapper -- cgit v1.2.3 From fdb6175aef0aa1896c6319d5425955ce0a5dc86b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Mar 2010 14:00:37 -0700 Subject: moved fifos around, now easier to see where they are and how big --- usrp2/top/u2_core/u2_core.v | 33 +++++++++++++++++++++++---------- usrp2/udp/udp_wrapper.v | 14 +++++++------- 2 files changed, 30 insertions(+), 17 deletions(-) (limited to 'usrp2/udp/udp_wrapper.v') diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 44715a04f..cd0199005 100644 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -144,6 +144,15 @@ module u2_core localparam SR_SIMTIMER = 198; // 2 localparam SR_TX_DSP = 208; // 16 localparam SR_TX_CTRL = 224; // 16 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + localparam DSP_TX_FIFOSIZE = 10; + localparam DSP_RX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 10; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? wire [7:0] set_addr; wire [31:0] set_data; @@ -440,24 +449,28 @@ module u2_core .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] buffer_udp; - wire udp_src_rdy, udp_dst_rdy; + wire [35:0] udp_tx_data, udp_rx_data; + wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), - .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy_o(wr2_ready_i), .rx_f36_dst_rdy_i(wr2_ready_o), -// .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy_i(rd2_ready_o), .tx_f36_dst_rdy_o(rd2_ready_i), - .tx_f36_data(buffer_udp), .tx_f36_src_rdy_i(udp_src_rdy), .tx_f36_dst_rdy_o(udp_dst_rdy), + .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), + .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), .debug(debug_udp) ); - fifo_cascade #(.WIDTH(36), .SIZE(10)) txudp_fifo_cascade + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(buffer_udp), .src_rdy_o(udp_src_rdy), .dst_rdy_i(udp_dst_rdy)); + .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus @@ -612,7 +625,7 @@ module u2_core .fifo_occupied(), .fifo_full(), .fifo_empty(), .debug_rx(vita_state) ); - fifo_cascade #(.WIDTH(36), .SIZE(10)) rx_fifo_cascade + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); @@ -626,7 +639,7 @@ module u2_core wire [31:0] debug_vtc, debug_vtd, debug_vt; - fifo_cascade #(.WIDTH(36), .SIZE(10)) tx_fifo_cascade + fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); @@ -660,7 +673,7 @@ module u2_core // /////////////////////////////////////////////////////////////////////////////////// // SERDES - serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes (.clk(dsp_clk),.rst(dsp_rst), .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), diff --git a/usrp2/udp/udp_wrapper.v b/usrp2/udp/udp_wrapper.v index 390abd0d5..f4c642615 100644 --- a/usrp2/udp/udp_wrapper.v +++ b/usrp2/udp/udp_wrapper.v @@ -1,7 +1,6 @@ module udp_wrapper - #(parameter BASE=0, - parameter RXFIFOSIZE=11) + #(parameter BASE=0) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o, @@ -44,8 +43,8 @@ module udp_wrapper wire rx_int2_src_rdy, rx_int2_dst_rdy; wire [18:0] rx_int2_data; - wire rx_int3_src_rdy, rx_int3_dst_rdy; - wire [35:0] rx_int3_data; + //wire rx_int3_src_rdy, rx_int3_dst_rdy; + //wire [35:0] rx_int3_data; `ifdef USE_PROT_ENG prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx @@ -68,15 +67,16 @@ module udp_wrapper fifo19_to_fifo36 fifo19_to_fifo36 (.clk(clk), .reset(reset), .clear(clear), .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy), - .f36_dataout(rx_int3_data), .f36_src_rdy_o(rx_int3_src_rdy), .f36_dst_rdy_i(rx_int3_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy_o), .f36_dst_rdy_i(rx_f36_dst_rdy_i), .debug(debug_state)); - + + /* fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo (.clk(clk), .reset(reset), .clear(clear), .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy), .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i), .space(), .occupied() ); - +*/ /* assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, -- cgit v1.2.3