From fdf98d12a58548a929ce44a860d8981c707f3ec7 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 9 Mar 2012 16:53:11 -0800 Subject: fifo ctrl: minor fixes for spi core, swap time define --- usrp2/top/N2x0/Makefile.N210R3 | 2 +- usrp2/top/N2x0/Makefile.N210R4 | 2 +- usrp2/top/USRP2/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'usrp2/top') diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3 index 3ef769d3a..411aa20f1 100644 --- a/usrp2/top/N2x0/Makefile.N210R3 +++ b/usrp2/top/N2x0/Makefile.N210R3 @@ -70,7 +70,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" " FIFO_CTRL_USE_TIME=1 $(CUSTOM_DEFS)" +"Verilog Macros" "$(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4 index 315388586..44ce17b3f 100644 --- a/usrp2/top/N2x0/Makefile.N210R4 +++ b/usrp2/top/N2x0/Makefile.N210R4 @@ -71,7 +71,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "LVDS=1 FIFO_CTRL_USE_TIME=1 $(CUSTOM_DEFS)" +"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile index 10610c7dc..94480a811 100644 --- a/usrp2/top/USRP2/Makefile +++ b/usrp2/top/USRP2/Makefile @@ -70,7 +70,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_DEFS)" +"Verilog Macros" "FIFO_CTRL_NO_TIME=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" -- cgit v1.2.3