From d4b6fa72eb3fec872a41dea136a5845d3c6ff1ec Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Thu, 19 Aug 2010 12:46:04 -0700 Subject: Regenerated FIFO with lower trigger level for almost full flag to reflect logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code. --- usrp2/top/u2_rev3/u2_core_udp.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'usrp2/top') diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index b0c8e6d52..c2811c833 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -648,11 +648,12 @@ module u2_core wire tx_src_rdy, tx_dst_rdy; wire [31:0] debug_vt; - ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.DEPTH(19)) + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(8)) ext_fifo_i1 ( .int_clk(dsp_clk), .ext_clk(clk_to_mac), +// .ext_clk(wb_clk), .rst(dsp_rst), .RAM_D_pi(RAM_D_pi), .RAM_D_po(RAM_D_po), -- cgit v1.2.3