From c407516349601831767952a9b12a077a2f23ea51 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 1 Feb 2012 09:47:07 -0800 Subject: dsp rework: paramaterize post_engine_buffering --- usrp2/top/N2x0/u2plus_core.v | 1 + usrp2/top/USRP2/u2_core.v | 1 + 2 files changed, 2 insertions(+) (limited to 'usrp2/top') diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index 0ee66d170..f04d449be 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -661,6 +661,7 @@ module u2plus_core wire strobe_tx; vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), + .POST_ENGINE_FIFOSIZE(DSP_TX_FIFOSIZE+1), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), .DSP_NUMBER(0)) diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 746853fbf..d29f31b8f 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -647,6 +647,7 @@ module u2_core wire strobe_tx; vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), + .POST_ENGINE_FIFOSIZE(DSP_TX_FIFOSIZE+1), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), .DSP_NUMBER(0)) -- cgit v1.2.3