From 8d1214d5a0279fec2dcd2e2c2b97ea60250cc6d4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 6 Oct 2010 18:15:17 -0700 Subject: reconnect GPIOs, remove debug pins, meets timing now --- usrp2/top/u2_rev3/u2_core_udp.v | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'usrp2/top') diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 2cf7fe5ee..4879cfc6b 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -414,7 +414,7 @@ module u2_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio(/* {io_tx,io_rx}*/ ) ); + .gpio({io_tx,io_rx}) ); // ///////////////////////////////////////////////////////////////////////// // Buffer Pool Status -- Slave #5 @@ -788,12 +788,10 @@ module u2_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins - assign debug_clk = {dsp_clk, clk_to_mac}; - assign debug = debug_extfifo; + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; // debug_extfifo; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; - assign {io_tx,io_rx} = debug_extfifo2; - endmodule // u2_core -- cgit v1.2.3