From 8a00096f9897fc6bb62e8fb7a5ce2fe336f91a8c Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 24 Apr 2012 20:02:02 -0700 Subject: b100: implement packet-end/flush cycle timeout --- usrp2/top/B100/u1plus_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/top') diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index c1d6767d1..74151ce98 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -413,7 +413,7 @@ module u1plus_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd3}; //major, minor + localparam compat_num = {16'd9, 16'd4}; //major, minor wire [31:0] reg_test32; -- cgit v1.2.3