From 89fc3946d6fa590dd8047984ed8718a6ffa4ab77 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 23 Feb 2010 16:35:06 -0800
Subject: use our fancy new debug ports

---
 usrp2/top/u1e/u1e_core.v | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'usrp2/top')

diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 7ac4c8f86..12c566b6c 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -206,6 +206,9 @@ module u1e_core
    assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
 		    { EM_D } };
 
+   assign debug_gpio_0 = { m0_we, m0_stb, m0_ack, s1_stb, s0_stb, m0_adr[10:0], m0_dat_mosi[15:0] };
+   assign debug_gpio_1 = { debug_txd, debug_rxd };
+   
    assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast;  // LEDs are arranged funny on board
    
 endmodule // u1e_core
-- 
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