From 7ffe28ccc6059ae3caa500e35b76718ae6ff100a Mon Sep 17 00:00:00 2001
From: Ian Buckley <ianb@server2.(none)>
Date: Tue, 14 Sep 2010 11:46:58 -0700
Subject: Enabled phase offset adjustment on DCM_INST1 which drives the
 external Fast SRAM clock. Set phase shift to -12 after experimentation using
 logic analyzer to see results. This value gives near optimum 1.5nS setup
 times on the source sync signals FPGA -> SRAM under lab conditions.

---
 usrp2/top/u2_rev3/u2_rev3.v | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

(limited to 'usrp2/top')

diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index e9f8d76eb..079a5cc4c 100644
--- a/usrp2/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -394,7 +394,7 @@ module u2_rev3
                   .PSCLK(1'b0), 
                   .PSEN(1'b0), 
                   .PSINCDEC(1'b0), 
-                  .RST(clk125_ext_RST_IN), 
+                  .RST(1'b0), 
                   .CLK0(clk125_ext_clk0), 
                   .CLK180(clk125_ext_clk180) );
    defparam DCM_INST1.CLK_FEEDBACK = "1X";
@@ -403,13 +403,13 @@ module u2_rev3
    defparam DCM_INST1.CLKFX_MULTIPLY = 4;
    defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE";
    defparam DCM_INST1.CLKIN_PERIOD = 8.000;
-   defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED";
    defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
    defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW";
    defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW";
    defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE";
    defparam DCM_INST1.FACTORY_JF = 16'h8080;
-   defparam DCM_INST1.PHASE_SHIFT = 0;
+   defparam DCM_INST1.PHASE_SHIFT = -12;
    defparam DCM_INST1.STARTUP_WAIT = "FALSE";
    
    IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), 
@@ -428,14 +428,14 @@ module u2_rev3
 			.R(1'b0),
 			.S(1'b0));
 
-   SRL16 dcm2_rst_i1 (.D(1'b0),
-		      .CLK(clk_to_mac_buf),
-		      .Q(dcm2_rst),
-		      .A0(1'b1),
-		      .A1(1'b1),
-		      .A2(1'b1),
-		      .A3(1'b1));
-   // synthesis attribute init of dcm2_rst_i2 is "000F";
+//   SRL16 dcm2_rst_i1 (.D(1'b0),
+//		      .CLK(clk_to_mac_buf),
+//		      .Q(dcm2_rst),
+//		      .A0(1'b1),
+//		      .A1(1'b1),
+//		      .A2(1'b1),
+//		      .A3(1'b1));
+   // synthesis attribute init of dcm2_rst_i1 is "000F";
       
    DCM DCM_INST2 (.CLKFB(clk125_int_buf), 
                   .CLKIN(clk_to_mac_buf), 
@@ -443,7 +443,7 @@ module u2_rev3
                   .PSCLK(1'b0), 
                   .PSEN(1'b0), 
                   .PSINCDEC(1'b0), 
-                  .RST(clk125_int_RST_IN),
+                  .RST(1'b0),
                   .CLK0(clk125_int));
    defparam DCM_INST2.CLK_FEEDBACK = "1X";
    defparam DCM_INST2.CLKDV_DIVIDE = 2.0;
-- 
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