From 4c111800a139a544f9280e1a7b114c027c55a89e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 1 Apr 2012 23:22:39 -0700 Subject: b100: fix slave fifo data xfer exit condition When exiting the read/write data state, when the transfer count maxes out/peaks, the fifo read/write signals were getting this condition the cycle after with the state change. --- usrp2/top/B100/u1plus_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/top') diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 26714b669..09b7e11f1 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -413,7 +413,7 @@ module u1plus_core // Readback mux 32 -- Slave #7 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd9, 16'd1}; //major, minor + localparam compat_num = {16'd9, 16'd2}; //major, minor wire [31:0] reg_test32; -- cgit v1.2.3