From 1a85baadf20a7e1a7e2789fd1a8947d27eeea08e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 16 Jul 2010 17:22:57 -0700 Subject: tx error packets now muxed into the ethernet stream back to the host --- usrp2/top/u2_rev3/u2_core_udp.v | 49 ++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 27 deletions(-) (limited to 'usrp2/top') diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index b034791a7..db74188a6 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -466,11 +466,20 @@ module u2_core .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), .debug(debug_udp) ); + wire [35:0] tx_err_data, udp1_tx_data; + wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(dsp_clk), .reset(dsp_reset), .clear(0), + .data0_i(), .src0_rdy_i(), .dst0_rdy_o(), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), @@ -639,40 +648,26 @@ module u2_core // DSP TX wire [35:0] tx_data; - wire [99:0] tx1_data; - wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy; - - wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); - vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), - .debug(debug_vtd) ); - - vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time),.underrun(underrun), - .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug(debug_vtc) ); - - assign debug_vt = debug_vtc | debug_vtd; - - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .tx_data_i(tx_err_data), .tx_src_rdy_i(tx_err_src_rdy), .tx_dst_rdy_o(tx_err_dst_rdy), .dac_a(dac_a),.dac_b(dac_b), - .debug(debug_tx_dsp) ); - + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + assign dsp_rst = wb_rst; // /////////////////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From 417c1d0abd5cbc52f46f2a3564b6805a59e6fe7f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 16 Jul 2010 17:25:49 -0700 Subject: fix a typo --- usrp2/top/u2_rev3/u2_core_udp.v | 2 +- usrp2/vrt/gen_context_pkt.v | 4 ++-- usrp2/vrt/vita_tx_chain.v | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'usrp2/top') diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index db74188a6..74359dad2 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -663,7 +663,7 @@ module u2_core .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), - .tx_data_i(tx_err_data), .tx_src_rdy_i(tx_err_src_rdy), .tx_dst_rdy_o(tx_err_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(dac_a),.dac_b(dac_b), .underrun(underrun), .run(run_tx), .debug(debug_vt)); diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 2fad43cc6..f413fdd1d 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -56,10 +56,10 @@ module gen_context_pkt CTXT_TICS : data_int <= { 2'b00, 32'd0 }; CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; CTXT_MESSAGE : data_int <= { 2'b10, message }; - default : {2'b00, 32'b00}; + default : data_int <= {2'b00, 32'b00}; endcase // case (ctxt_state) - fifo_short (.WIDTH(34)) ctxt_fifo + fifo_short #(.WIDTH(34)) ctxt_fifo (.clk(clk), .reset(reset), .clear(clear), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 66f775ddf..cc091f2d5 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -8,7 +8,7 @@ module vita_tx_chain input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o, - input [35:0] err_data_i, input err_src_rdy_i, output err_dst_rdy_o, + output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i, output [15:0] dac_a, output [15:0] dac_b, output underrun, output run, output [31:0] debug); -- cgit v1.2.3 From 908b8bd5ebee54e55361679d57ebca3b21c594b5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 16 Jul 2010 17:42:14 -0700 Subject: connect the demux --- usrp2/top/u2_rev3/u2_core_udp.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/top') diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 74359dad2..b79cab5fb 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -476,7 +476,7 @@ module u2_core fifo36_mux #(.prio(0)) mux_err_stream (.clk(dsp_clk), .reset(dsp_reset), .clear(0), - .data0_i(), .src0_rdy_i(), .dst0_rdy_o(), + .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); -- cgit v1.2.3 From 52a1e1c10b3298ad689e88fd9d8ccdd94d08f56b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 9 Aug 2010 17:33:50 -0700 Subject: makefile dependency fix for second expansion --- usrp2/top/Makefile.common | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/top') diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index d0435fa1e..4da64ac28 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -47,7 +47,7 @@ $(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST) @echo $@ $(ISE_HELPER) "" -$(BIN_FILE): $(ISE_FILE) +$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST) @echo $@ $(ISE_HELPER) "Generate Programming File" touch $@ -- cgit v1.2.3 From 0f0e3abe76c88bee67e278952c1db4ae59c624be Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 9 Aug 2010 18:18:04 -0700 Subject: added compat number to usrp2 readback mux --- usrp2/top/u2_rev3/u2_core_udp.v | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'usrp2/top') diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index b79cab5fb..124930c23 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -423,7 +423,10 @@ module u2_core cycle_count <= 0; else cycle_count <= cycle_count + 1; - + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd1; + wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), @@ -431,7 +434,7 @@ module u2_core .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From 7c057ae28c7dda5f60944fdf79c2bafa081b9bfe Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 25 Aug 2010 17:44:17 -0700 Subject: Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future --- usrp2/sdr_lib/dsp_core_rx.v | 35 +++++++++++++---------------------- usrp2/top/u2_rev3/u2_core_udp.v | 2 +- usrp2/top/u2_rev3/u2_rev3.v | 8 ++++---- 3 files changed, 18 insertions(+), 27 deletions(-) (limited to 'usrp2/top') diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index 1e689fc7f..1318809d6 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -57,41 +57,32 @@ module dsp_core_rx (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_in(adc_b),.adc_out(adc_b_ofs)); - wire [3:0] muxctrl; - setting_reg #(.my_addr(BASE+5)) sr_8 + wire [7:0] muxctrl; + setting_reg #(.my_addr(BASE+5), .width(8)) sr_8 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({UNUSED_2,muxctrl}),.changed()); wire [1:0] gpio_ena; - setting_reg #(.my_addr(BASE+6)) sr_9 + setting_reg #(.my_addr(BASE+6), .width(2)) sr_9 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({UNUSED_3,gpio_ena}),.changed()); - // The TVRX connects to what is called adc_b, thus A and B are - // swapped throughout the design. - // - // In the interest of expediency and keeping the s/w sane, we just remap them here. - // The I & Q fields are mapped the same: - // 0 -> "the real A" (as determined by the TVRX) - // 1 -> "the real B" - // 2 -> const zero - always @(posedge clk) - case(muxctrl[1:0]) // The I mapping - 0: adc_i <= adc_b_ofs; // "the real A" - 1: adc_i <= adc_a_ofs; + case(muxctrl[3:0]) // The I mapping + 0: adc_i <= adc_a_ofs; + 1: adc_i <= adc_b_ofs; 2: adc_i <= 0; default: adc_i <= 0; - endcase // case(muxctrl[1:0]) - + endcase // case (muxctrl[3:0]) + always @(posedge clk) - case(muxctrl[3:2]) // The Q mapping - 0: adc_q <= adc_b_ofs; // "the real A" - 1: adc_q <= adc_a_ofs; + case(muxctrl[7:4]) // The Q mapping + 0: adc_q <= adc_a_ofs; + 1: adc_q <= adc_b_ofs; 2: adc_q <= 0; default: adc_q <= 0; - endcase // case(muxctrl[3:2]) - + endcase // case (muxctrl[7:4]) + always @(posedge clk) if(rst) phase <= 0; diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index 124930c23..c9502898b 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -425,7 +425,7 @@ module u2_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd1; + localparam compat_num = 32'd2; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 3a43e4ffe..d5b382c19 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -205,10 +205,10 @@ module u2_rev3 always @(posedge dsp_clk) begin - adc_a_reg1 <= adc_a; - adc_b_reg1 <= adc_b; - adc_ovf_a_reg1 <= adc_ovf_a; - adc_ovf_b_reg1 <= adc_ovf_b; + adc_a_reg1 <= adc_b; // I and Q on RX are swapped in layout + adc_b_reg1 <= adc_a; + adc_ovf_a_reg1 <= adc_ovf_b; + adc_ovf_b_reg1 <= adc_ovf_a; end always @(posedge dsp_clk) -- cgit v1.2.3 From 9fa6105a49f41e39321438086b00ab12d8437828 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 25 Aug 2010 17:57:06 -0700 Subject: clean up DAC inversion and swapping to match schematics --- usrp2/top/u2_rev3/u2_rev3.v | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'usrp2/top') diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index d5b382c19..4daa66212 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -203,9 +203,10 @@ module u2_rev3 reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + // ADC A and B are swapped in schematic to facilitate clean layout always @(posedge dsp_clk) begin - adc_a_reg1 <= adc_b; // I and Q on RX are swapped in layout + adc_a_reg1 <= adc_b; adc_b_reg1 <= adc_a; adc_ovf_a_reg1 <= adc_ovf_b; adc_ovf_b_reg1 <= adc_ovf_a; @@ -327,8 +328,10 @@ module u2_rev3 end wire [15:0] dac_a_int, dac_b_int; - always @(negedge dsp_clk) dac_a <= dac_a_int; - always @(negedge dsp_clk) dac_b <= dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(negedge dsp_clk) dac_a <= ~dac_b_int; + always @(negedge dsp_clk) dac_b <= dac_a_int; /* OFDDRRSE OFDDRRSE_serdes_inst -- cgit v1.2.3