From fb704918b285a7d039cda27daf35f628442a7dca Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 9 Jun 2010 18:25:35 -0700
Subject: actually generates an image
---
usrp2/top/u2plus/Makefile | 6 +++---
usrp2/top/u2plus/u2plus.ucf | 3 ---
usrp2/top/u2plus/u2plus.v | 17 ++++++-----------
3 files changed, 9 insertions(+), 17 deletions(-)
(limited to 'usrp2/top/u2plus')
diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile
index 29928e03e..777a03662 100644
--- a/usrp2/top/u2plus/Makefile
+++ b/usrp2/top/u2plus/Makefile
@@ -29,7 +29,7 @@ ISE_HELPER := ../tcl/ise_helper.tcl
##################################################
# Project Setup
##################################################
-BUILD_DIR := build/
+BUILD_DIR := build$(ISE)/
export TOP_MODULE := u2plus
export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
@@ -172,7 +172,7 @@ sdr_lib/clip_reg.v \
sdr_lib/cordic.v \
sdr_lib/cordic_z24.v \
sdr_lib/cordic_stage.v \
-sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_rx_udp.v \
sdr_lib/dsp_core_tx.v \
sdr_lib/hb_dec.v \
sdr_lib/hb_interp.v \
@@ -196,7 +196,7 @@ timing/time_sender.v \
timing/time_sync.v \
timing/timer.v \
timing/simple_timer.v \
-top/u2_core/u2_core.v \
+top/u2plus/u2plus_core.v \
top/u2plus/capture_ddrlvds.v \
top/u2plus/u2plus.ucf \
top/u2plus/u2plus.v
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
index a3cd61906..00838e19d 100755
--- a/usrp2/top/u2plus/u2plus.ucf
+++ b/usrp2/top/u2plus/u2plus.ucf
@@ -407,9 +407,6 @@ TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
-NET "cpld_clk" TNM_NET = "cpld_clk";
-TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
-
NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index fef23af60..13c7a811f 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -286,7 +286,7 @@ module u2plus
.S(0) // Synchronous preset input
);
*/
- u2_core u2_core(.dsp_clk (dsp_clk),
+ u2plus_core u2p_c(.dsp_clk (dsp_clk),
.wb_clk (wb_clk),
.clock_ready (clock_ready),
.clk_to_mac (clk_to_mac),
@@ -323,12 +323,6 @@ module u2plus
.ser_r (ser_r_int[15:0]),
.ser_rklsb (ser_rklsb_int),
.ser_rkmsb (ser_rkmsb_int),
- .cpld_start (cpld_start),
- .cpld_mode (cpld_mode),
- .cpld_done (cpld_done),
- .cpld_din (cpld_din),
- .cpld_clk (cpld_clk),
- .cpld_detached (cpld_detached),
.adc_a (adc_a[13:0]),
.adc_ovf_a (adc_ovf_a),
.adc_on_a (adc_on_a),
@@ -374,13 +368,14 @@ module u2plus
.uart_rx_i (uart_rx_i),
.uart_baud_o (),
.sim_mode (1'b0),
- .clock_divider (2)
+ .clock_divider (2),
+ .spiflash_cs (flash_cs),
+ .spiflash_clk (flash_clk),
+ .spiflash_miso (flash_miso),
+ .spiflash_mosi (flash_mosi)
);
assign RAM_ZZ = 1;
- assign flash_clk = 0;
- assign flash_cs = 1;
- assign flash_mosi = 0;
assign RAM_BWn = 4'b1111;
assign TXD = 3'b111;
--
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