From 9e2e78642251ee9e024461becfd70a75b11d818a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 25 Aug 2010 19:00:02 -0700 Subject: SWAP DAC A and B, invert B to match schematics --- usrp2/top/u2plus/u2plus.v | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'usrp2/top/u2plus') diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index d330e336b..db31b4a68 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -298,10 +298,11 @@ module u2plus */ wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(negedge dsp_clk) DACA <= ~dac_b_int; + always @(negedge dsp_clk) DACB <= dac_a_int; - always @(negedge dsp_clk) DACA <= dac_a_int; - always @(negedge dsp_clk) DACB <= dac_b_int; - u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), -- cgit v1.2.3