From b7e1b9ce77a0df46a5b336fda1e1972aa8199488 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 7 Jun 2010 14:22:30 -0700 Subject: compiles now, added clock constraints --- usrp2/top/u2plus/u2plus.ucf | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'usrp2/top/u2plus/u2plus.ucf') diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf index 31404dda9..a3cd61906 100755 --- a/usrp2/top/u2plus/u2plus.ucf +++ b/usrp2/top/u2plus/u2plus.ucf @@ -399,3 +399,21 @@ NET "flash_cs" LOC = "AA7" ; #NET "unnamed_net11" LOC = "G7" ; # TDI #NET "unnamed_net10" LOC = "A25" ; # TCK #NET "unnamed_net20" LOC = "V20" ; # SUSPEND + + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; -- cgit v1.2.3