From b774533c615ef34732d93c30a6df6fa4d702d90e Mon Sep 17 00:00:00 2001 From: Johnathan Corgan Date: Tue, 23 Feb 2010 08:27:29 -0800 Subject: Manually assign clk_fpga to BUFG to improve timing Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs --- usrp2/top/u2_rev3/u2_rev3.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'usrp2/top/u2_rev3') diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 23a825007..3c35743a3 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -171,7 +171,11 @@ module u2_rev3 wd <= wd + 1; assign WDI = wd[15]; - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + wire clk_fpga_unbuf; + + IBUFGDS clk_fpga_pin (.O(clk_fpga_unbuf),.I(clk_fpga_p),.IB(clk_fpga_n)); + BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; wire exp_pps_in; -- cgit v1.2.3 From 06ba14e55b200b9aa0314f63b38c08f30613859f Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Wed, 24 Feb 2010 10:54:54 -0800 Subject: Cut debug bus connection to etherenet MAC to make closing timing easier --- usrp2/top/u2_rev3/u2_rev3.v | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'usrp2/top/u2_rev3') diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 3c35743a3..3a43e4ffe 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -177,6 +177,9 @@ module u2_rev3 BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf)); defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire cpld_clock_buf; + BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock)); wire exp_pps_in; IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); @@ -314,7 +317,9 @@ module u2_rev3 reg [15:0] ser_r_int; reg ser_rklsb_int, ser_rkmsb_int; - always @(posedge ser_rx_clk) + wire ser_rx_clk_buf; + BUFG ser_rx_clk_BUF (.O(ser_rx_clk_buf),.I(ser_rx_clk)); + always @(posedge ser_rx_clk_buf) begin ser_r_int <= ser_r; ser_rklsb_int <= ser_rklsb; @@ -371,7 +376,7 @@ module u2_rev3 .ser_t (ser_t_unreg[15:0]), .ser_tklsb (ser_tklsb_unreg), .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), + .ser_rx_clk (ser_rx_clk_buf), .ser_r (ser_r_int[15:0]), .ser_rklsb (ser_rklsb_int), .ser_rkmsb (ser_rkmsb_int), -- cgit v1.2.3 From 50b1ca13e651152a731d3fdf7a5f532b65e04e13 Mon Sep 17 00:00:00 2001 From: Johnathan Corgan Date: Mon, 29 Mar 2010 15:35:06 -0700 Subject: Added timing constraint for Wishbone clock/dsp_clock skew --- usrp2/top/u2_rev3/u2_rev3.ucf | 2 ++ 1 file changed, 2 insertions(+) (limited to 'usrp2/top/u2_rev3') diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index 255a298ac..6aa699d2a 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -331,3 +331,5 @@ NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; #NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; #NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; -- cgit v1.2.3 From de21671b8dab89d6aaa3b6bbb99a4dc0d306121f Mon Sep 17 00:00:00 2001 From: Johnathan Corgan Date: Mon, 29 Mar 2010 17:14:24 -0700 Subject: Update config to all eight clock buffers to be used. --- usrp2/top/u2_rev3/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/top/u2_rev3') diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 4358d7c56..81d787566 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -183,7 +183,7 @@ top/u2_rev3/u2_rev3.v # Process Properties ################################################## export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ +"Number of Clock Buffers" 8 \ "Pack I/O Registers into IOBs" Yes \ "Optimization Effort" High \ "Optimize Instantiated Primitives" TRUE \ -- cgit v1.2.3