From 1fbf547c27634994b0b48df49b06b4c40bc763c7 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 17 Feb 2011 13:33:32 -0800
Subject: u2/u2p: reduce unneeded RX DSP buffering
---
usrp2/top/u2_rev3/u2_core.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'usrp2/top/u2_rev3')
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index 7dce8c673..1f422a1f1 100644
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -153,7 +153,7 @@ module u2_core
// FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
// all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
localparam DSP_TX_FIFOSIZE = 10;
- localparam DSP_RX_FIFOSIZE = 10;
+ localparam DSP_RX_FIFOSIZE = 9;
localparam ETH_TX_FIFOSIZE = 10;
localparam ETH_RX_FIFOSIZE = 11;
localparam SERDES_TX_FIFOSIZE = 9;
--
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