From c5295159e9f6eeb9ea72edab18ff97eb55d84692 Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Wed, 1 Sep 2010 03:08:11 -0700 Subject: Added to DCM's and some BUFG's to align the internal 125MHz clock edge with its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet. --- usrp2/top/u2_rev3/u2_rev3.ucf | 1 + 1 file changed, 1 insertion(+) (limited to 'usrp2/top/u2_rev3/u2_rev3.ucf') diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf index bf9569fe4..175fbec8d 100644 --- a/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/usrp2/top/u2_rev3/u2_rev3.ucf @@ -324,6 +324,7 @@ NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; +NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; #NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; #NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; -- cgit v1.2.3