From b48b0f171b9e24c161efc6d2b1d2b1a1dbb0324d Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Sat, 31 Jul 2010 00:15:16 -0700 Subject: External FIFO tested in simulation and on USRP2 from decimation 64->8 with current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched. --- usrp2/top/u2_rev3/Makefile.udp | 2 ++ 1 file changed, 2 insertions(+) (limited to 'usrp2/top/u2_rev3/Makefile.udp') diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp index 9962887d4..99effb038 100644 --- a/usrp2/top/u2_rev3/Makefile.udp +++ b/usrp2/top/u2_rev3/Makefile.udp @@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extram/Makefile.srcs +include ../../extramfifo/Makefile.srcs + ################################################## # Project Properties -- cgit v1.2.3