From 45e5589ed9c555c604fb66be9f314c02ff5fb9e4 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 10 Jun 2010 11:34:18 -0700
Subject: first attempt at cleaning up the build system

---
 usrp2/top/u2_rev3/Makefile.udp | 238 ++++++-----------------------------------
 1 file changed, 32 insertions(+), 206 deletions(-)

(limited to 'usrp2/top/u2_rev3/Makefile.udp')

diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp
index f6e6e5b15..90a5d88be 100644
--- a/usrp2/top/u2_rev3/Makefile.udp
+++ b/usrp2/top/u2_rev3/Makefile.udp
@@ -1,42 +1,30 @@
 #
 # Copyright 2008 Ettus Research LLC
-# 
-# This file is part of GNU Radio
-# 
-# GNU Radio is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-# 
-# GNU Radio is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with GNU Radio; see the file COPYING.  If not, write to
-# the Free Software Foundation, Inc., 51 Franklin Street,
-# Boston, MA 02110-1301, USA.
-# 
+#
 
-##################################################
-# xtclsh Shell and tcl Script Path
-##################################################
-#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
-XTCLSH := xtclsh
-ISE_HELPER := ../tcl/ise_helper.tcl
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
 
 ##################################################
 # Project Setup
 ##################################################
-BUILD_DIR := build-udp$(ISE)/
-export TOP_MODULE := u2_rev3
-export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+TOP_MODULE = u2_rev3
+BUILD_DIR = $(abspath build-udp$(ISE))
 
 ##################################################
 # Project Properties
 ##################################################
-export PROJECT_PROPERTIES := \
+PROJECT_PROPERTIES = \
 family Spartan3 \
 device xc3s2000 \
 package fg456 \
@@ -51,159 +39,20 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 ##################################################
 # Sources
 ##################################################
-export SOURCE_ROOT := ../../../
-export SOURCES := \
-control_lib/CRC16_D16.v \
-control_lib/atr_controller.v \
-control_lib/bin2gray.v \
-control_lib/dcache.v \
-control_lib/decoder_3_8.v \
-control_lib/dpram32.v \
-control_lib/gray2bin.v \
-control_lib/gray_send.v \
-control_lib/icache.v \
-control_lib/mux4.v \
-control_lib/mux8.v \
-control_lib/nsgpio.v \
-control_lib/ram_2port.v \
-control_lib/ram_harv_cache.v \
-control_lib/ram_loader.v \
-control_lib/setting_reg.v \
-control_lib/settings_bus.v \
-control_lib/settings_bus_crossclock.v \
-control_lib/srl.v \
-control_lib/system_control.v \
-control_lib/wb_1master.v \
-control_lib/wb_readback_mux.v \
-control_lib/simple_uart.v \
-control_lib/simple_uart_tx.v \
-control_lib/simple_uart_rx.v \
-control_lib/oneshot_2clk.v \
-control_lib/sd_spi.v \
-control_lib/sd_spi_wb.v \
-control_lib/wb_bridge_16_32.v \
-control_lib/reset_sync.v \
-control_lib/priority_enc.v \
-control_lib/pic.v \
-vrt/vita_rx_control.v \
-vrt/vita_rx_framer.v \
-vrt/vita_tx_control.v \
-vrt/vita_tx_deframer.v \
-udp/udp_wrapper.v \
-udp/fifo19_rxrealign.v \
-udp/prot_eng_tx.v \
-udp/add_onescomp.v \
-simple_gemac/simple_gemac_wrapper.v \
-simple_gemac/simple_gemac_wrapper19.v \
-simple_gemac/simple_gemac.v \
-simple_gemac/simple_gemac_wb.v \
-simple_gemac/simple_gemac_tx.v \
-simple_gemac/simple_gemac_rx.v \
-simple_gemac/crc.v \
-simple_gemac/delay_line.v \
-simple_gemac/flow_ctrl_tx.v \
-simple_gemac/flow_ctrl_rx.v \
-simple_gemac/address_filter.v \
-simple_gemac/ll8_to_txmac.v \
-simple_gemac/rxmac_to_ll8.v \
-simple_gemac/miim/eth_miim.v \
-simple_gemac/miim/eth_clockgen.v \
-simple_gemac/miim/eth_outputcontrol.v \
-simple_gemac/miim/eth_shiftreg.v \
-control_lib/newfifo/buffer_int.v \
-control_lib/newfifo/buffer_pool.v \
-control_lib/newfifo/fifo_2clock.v \
-control_lib/newfifo/fifo_2clock_cascade.v \
-control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/fifo_short.v \
-control_lib/newfifo/fifo_long.v \
-control_lib/newfifo/fifo_cascade.v \
-control_lib/newfifo/fifo36_to_ll8.v \
-control_lib/newfifo/ll8_to_fifo36.v \
-control_lib/newfifo/fifo19_to_ll8.v \
-control_lib/newfifo/ll8_to_fifo19.v \
-control_lib/newfifo/fifo36_to_fifo19.v \
-control_lib/newfifo/fifo19_to_fifo36.v \
-control_lib/longfifo.v \
-control_lib/shortfifo.v \
-control_lib/medfifo.v \
-coregen/fifo_xlnx_2Kx36_2clk.v \
-coregen/fifo_xlnx_2Kx36_2clk.xco \
-coregen/fifo_xlnx_512x36_2clk.v \
-coregen/fifo_xlnx_512x36_2clk.xco \
-coregen/fifo_xlnx_64x36_2clk.v \
-coregen/fifo_xlnx_64x36_2clk.xco \
-coregen/fifo_xlnx_16x19_2clk.v \
-coregen/fifo_xlnx_16x19_2clk.xco \
-coregen/fifo_xlnx_16x40_2clk.v \
-coregen/fifo_xlnx_16x40_2clk.xco \
-extram/wb_zbt16_b.v \
-opencores/8b10b/decode_8b10b.v \
-opencores/8b10b/encode_8b10b.v \
-opencores/aemb/rtl/verilog/aeMB_bpcu.v \
-opencores/aemb/rtl/verilog/aeMB_core_BE.v \
-opencores/aemb/rtl/verilog/aeMB_ctrl.v \
-opencores/aemb/rtl/verilog/aeMB_edk32.v \
-opencores/aemb/rtl/verilog/aeMB_ibuf.v \
-opencores/aemb/rtl/verilog/aeMB_regf.v \
-opencores/aemb/rtl/verilog/aeMB_xecu.v \
-opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_defines.v \
-opencores/i2c/rtl/verilog/i2c_master_top.v \
-opencores/i2c/rtl/verilog/timescale.v \
-opencores/spi/rtl/verilog/spi_clgen.v \
-opencores/spi/rtl/verilog/spi_defines.v \
-opencores/spi/rtl/verilog/spi_shift.v \
-opencores/spi/rtl/verilog/spi_top.v \
-opencores/spi/rtl/verilog/timescale.v \
-sdr_lib/acc.v \
-sdr_lib/add2.v \
-sdr_lib/add2_and_round.v \
-sdr_lib/add2_and_round_reg.v \
-sdr_lib/add2_reg.v \
-sdr_lib/cic_dec_shifter.v \
-sdr_lib/cic_decim.v \
-sdr_lib/cic_int_shifter.v \
-sdr_lib/cic_interp.v \
-sdr_lib/cic_strober.v \
-sdr_lib/clip.v \
-sdr_lib/clip_reg.v \
-sdr_lib/cordic.v \
-sdr_lib/cordic_z24.v \
-sdr_lib/cordic_stage.v \
-sdr_lib/dsp_core_rx_udp.v \
-sdr_lib/dsp_core_tx.v \
-sdr_lib/hb_dec.v \
-sdr_lib/hb_interp.v \
-sdr_lib/round.v \
-sdr_lib/round_reg.v \
-sdr_lib/rx_control.v \
-sdr_lib/rx_dcoffset.v \
-sdr_lib/sign_extend.v \
-sdr_lib/small_hb_dec.v \
-sdr_lib/small_hb_int.v \
-sdr_lib/tx_control.v \
-serdes/serdes.v \
-serdes/serdes_fc_rx.v \
-serdes/serdes_fc_tx.v \
-serdes/serdes_rx.v \
-serdes/serdes_tx.v \
-timing/time_64bit.v \
-timing/time_compare.v \
-timing/time_receiver.v \
-timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
-timing/simple_timer.v \
-top/u2_rev3/u2_core_udp.v \
-top/u2_rev3/u2_rev3.ucf \
-top/u2_rev3/u2_rev3.v 
+TOP_SRCS = \
+u2_core_udp.v \
+u2_rev3.v \
+u2_rev3.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
 
 ##################################################
 # Process Properties
 ##################################################
-export SYNTHESIZE_PROPERTIES := \
+SYNTHESIZE_PROPERTIES = \
 "Number of Clock Buffers" 8 \
 "Pack I/O Registers into IOBs" Yes \
 "Optimization Effort" High \
@@ -213,10 +62,10 @@ export SYNTHESIZE_PROPERTIES := \
 "Use Synchronous Reset" Auto \
 "Use Synchronous Set" Auto
 
-export TRANSLATE_PROPERTIES := \
+TRANSLATE_PROPERTIES = \
 "Macro Search Path" "$(shell pwd)/../../coregen/"
 
-export MAP_PROPERTIES := \
+MAP_PROPERTIES = \
 "Allow Logic Optimization Across Hierarchy" TRUE \
 "Map to Input Functions" 4 \
 "Optimization Strategy (Cover Mode)" Speed \
@@ -227,41 +76,18 @@ export MAP_PROPERTIES := \
 "Combinatorial Logic Optimization" TRUE \
 "Register Duplication" TRUE
 
-export PLACE_ROUTE_PROPERTIES := \
+PLACE_ROUTE_PROPERTIES = \
 "Place & Route Effort Level (Overall)" High 
 
-export STATIC_TIMING_PROPERTIES := \
+STATIC_TIMING_PROPERTIES = \
 "Number of Paths in Error/Verbose Report" 10 \
 "Report Type" "Error Report"
 
-export GEN_PROG_FILE_PROPERTIES := \
+GEN_PROG_FILE_PROPERTIES = \
 "Configuration Rate" 6 \
 "Create Binary Configuration File" TRUE \
 "Done (Output Events)" 5 \
 "Enable Bitstream Compression" TRUE \
 "Enable Outputs (Output Events)" 6 
 
-export SIM_MODEL_PROPERTIES := ""
-
-##################################################
-# Make Options
-##################################################
-all:
-	@echo make proj, check, synth, bin, or clean
-
-proj:
-	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
-
-check:
-	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
-
-synth:
-	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
-
-bin:
-	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
-
-clean:
-	rm -rf $(BUILD_DIR)
-
-
+SIM_MODEL_PROPERTIES = ""
-- 
cgit v1.2.3


From 1935f2a4ed0d0abc90bb3fe7fed745ff84ab6d7c Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 11 Jun 2010 17:23:34 -0700
Subject: produces good bin files

---
 usrp2/top/Makefile.common      | 39 +++------------------------------------
 usrp2/top/tcl/ise_helper.tcl   | 17 ++++++++---------
 usrp2/top/u2_rev3/Makefile     | 16 ++++++++++------
 usrp2/top/u2_rev3/Makefile.udp | 16 ++++++++++------
 4 files changed, 31 insertions(+), 57 deletions(-)

(limited to 'usrp2/top/u2_rev3/Makefile.udp')

diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common
index 25c48d31a..02b1b9529 100644
--- a/usrp2/top/Makefile.common
+++ b/usrp2/top/Makefile.common
@@ -6,15 +6,10 @@
 # Constants
 ##################################################
 BASE_DIR = $(abspath ..)
-ISE_HELPER = xtclsh /home/matt/sourcerepo/mobfleet/system_board/fpga/scripts/ise_helper.tcl
-#ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
+ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
 ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).ise
-BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit
-MAKE_ACE = $(BUILD_DIR)/make_ace.cmd
-ACE_FILE = $(BUILD_DIR)/xilinx.sys
+BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin
 MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs
-IMPACT_CMD = $(BUILD_DIR)/impact.cmd
-IMPACT_CDF = $(BUILD_DIR)/impact.cdf
 
 ##################################################
 # Global Targets
@@ -31,18 +26,12 @@ synth: $(ISE_FILE)
 
 bin: $(BIN_FILE)
 
-ace: $(ACE_FILE)
-
 mcs: $(MCS_FILE)
 
 clean:
 	$(RM) -r $(BUILD_DIR)
 
-XIL_IMPACT_USE_LIBUSB=1
-jtag-install: $(IMPACT_CMD)
-	impact -batch $<
-
-.PHONY: all proj check synth bin ace mcs clean jtag-install
+.PHONY: all proj check synth bin mcs clean
 
 ##################################################
 # Dependency Targets
@@ -56,29 +45,7 @@ $(BIN_FILE): $(ISE_FILE)
 	$(ISE_HELPER) "Generate Programming File"
 	touch $@
 
-$(MAKE_ACE): $(BASE_DIR)/scripts/make_ace.cmd.in
-	sed \
-		-e 's|@BUILD_DIR[@]|$(BUILD_DIR)|g' \
-		-e 's|@TOP_MODULE[@]|$(TOP_MODULE)|g' \
-		-e 's|@BIN_FILE[@]|$(BIN_FILE)|g' \
-	$< > $@
-
-$(ACE_FILE): $(BIN_FILE) $(MAKE_ACE)
-	@echo $@
-	impact -batch $(MAKE_ACE)
-
 $(MCS_FILE): $(BIN_FILE)
 	promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIN_FILE)
 
-$(IMPACT_CDF): $(BASE_DIR)/scripts/impact.cdf.in
-	sed \
-		-e 's|@BIN_FILE[@]|$(BIN_FILE)|g' \
-	$< > $@
-
-$(IMPACT_CMD): $(BASE_DIR)/scripts/impact.cmd.in $(IMPACT_CDF)
-	sed \
-		-e 's|@PART_NAME[@]|xc5vsx50t|g' \
-		-e 's|@CDF_FILE[@]|$(IMPACT_CDF)|g' \
-	$< > $@
-
 .EXPORT_ALL_VARIABLES:
diff --git a/usrp2/top/tcl/ise_helper.tcl b/usrp2/top/tcl/ise_helper.tcl
index fe9db87af..a4bee76b8 100644
--- a/usrp2/top/tcl/ise_helper.tcl
+++ b/usrp2/top/tcl/ise_helper.tcl
@@ -40,12 +40,12 @@ proc set_props {process options} {
 	}
 }
 
-if [file isfile $env(PROJ_FILE)] {
-	puts ">>> Opening project: $env(PROJ_FILE)"
-	project open $env(PROJ_FILE)
+if [file isfile $env(ISE_FILE)] {
+	puts ">>> Opening project: $env(ISE_FILE)"
+	project open $env(ISE_FILE)
 } else {	
-	puts ">>> Creating project: $env(PROJ_FILE)"
-	project new $env(PROJ_FILE)
+	puts ">>> Creating project: $env(ISE_FILE)"
+	project new $env(ISE_FILE)
 	
 	##################################################
 	# Set the project properties
@@ -56,7 +56,6 @@ if [file isfile $env(PROJ_FILE)] {
 	# Add the sources
 	##################################################
 	foreach source $env(SOURCES) {
-		set source $env(SOURCE_ROOT)$source
 		puts ">>> Adding source to project: $source"
 		xfile add $source
 	}
@@ -78,9 +77,9 @@ if [file isfile $env(PROJ_FILE)] {
 	set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES)
 }
 
-if [string compare $env(PROCESS_RUN) ""] {
-	puts ">>> Running Process: $env(PROCESS_RUN)"
-	process run $env(PROCESS_RUN)
+if [string compare [lindex $argv 0] ""] {
+	puts ">>> Running Process: [lindex $argv 0]"
+	process run [lindex $argv 0]
 }
 
 project close
diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile
index 86e5bf979..68c296b9b 100644
--- a/usrp2/top/u2_rev3/Makefile
+++ b/usrp2/top/u2_rev3/Makefile
@@ -2,6 +2,16 @@
 # Copyright 2008 Ettus Research LLC
 #
 
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u2_rev3
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
 include ../Makefile.common
 include ../../fifo/Makefile.srcs
 include ../../control_lib/Makefile.srcs
@@ -15,12 +25,6 @@ include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../extram/Makefile.srcs
 
-##################################################
-# Project Setup
-##################################################
-TOP_MODULE = u2_rev3
-BUILD_DIR = $(abspath build$(ISE))
-
 ##################################################
 # Project Properties
 ##################################################
diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp
index 90a5d88be..9962887d4 100644
--- a/usrp2/top/u2_rev3/Makefile.udp
+++ b/usrp2/top/u2_rev3/Makefile.udp
@@ -2,6 +2,16 @@
 # Copyright 2008 Ettus Research LLC
 #
 
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u2_rev3
+BUILD_DIR = $(abspath build-udp$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
 include ../Makefile.common
 include ../../fifo/Makefile.srcs
 include ../../control_lib/Makefile.srcs
@@ -15,12 +25,6 @@ include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../extram/Makefile.srcs
 
-##################################################
-# Project Setup
-##################################################
-TOP_MODULE = u2_rev3
-BUILD_DIR = $(abspath build-udp$(ISE))
-
 ##################################################
 # Project Properties
 ##################################################
-- 
cgit v1.2.3