From f0a9f021120eae604321edb9a97a7a5d8716da47 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 7 Jun 2011 16:26:30 -0700 Subject: remove old ethernet tester, no longer needed or working --- usrp2/top/u1e_ethdebug/.gitignore | 6 --- usrp2/top/u1e_ethdebug/Makefile | 83 ------------------------------------ usrp2/top/u1e_ethdebug/u1e.ucf | 88 --------------------------------------- usrp2/top/u1e_ethdebug/u1e.v | 28 ------------- 4 files changed, 205 deletions(-) delete mode 100644 usrp2/top/u1e_ethdebug/.gitignore delete mode 100644 usrp2/top/u1e_ethdebug/Makefile delete mode 100644 usrp2/top/u1e_ethdebug/u1e.ucf delete mode 100644 usrp2/top/u1e_ethdebug/u1e.v (limited to 'usrp2/top/u1e_ethdebug') diff --git a/usrp2/top/u1e_ethdebug/.gitignore b/usrp2/top/u1e_ethdebug/.gitignore deleted file mode 100644 index 8d872713e..000000000 --- a/usrp2/top/u1e_ethdebug/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -*~ -build -*.log -*.cmd -tb_u1e -*.lxt diff --git a/usrp2/top/u1e_ethdebug/Makefile b/usrp2/top/u1e_ethdebug/Makefile deleted file mode 100644 index 751b52970..000000000 --- a/usrp2/top/u1e_ethdebug/Makefile +++ /dev/null @@ -1,83 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u1e -BUILD_DIR = $(abspath build$(ISE)) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package cs484 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u1e.v \ -u1e.ucf - -SOURCES = $(abspath $(TOP_SRCS)) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u1e_ethdebug/u1e.ucf b/usrp2/top/u1e_ethdebug/u1e.ucf deleted file mode 100644 index d6a2ea4ed..000000000 --- a/usrp2/top/u1e_ethdebug/u1e.ucf +++ /dev/null @@ -1,88 +0,0 @@ - -## GPMC -NET "EM_D<15>" LOC = "D13" ; -NET "EM_D<14>" LOC = "D15" ; -NET "EM_D<13>" LOC = "C16" ; -NET "EM_D<12>" LOC = "B20" ; -NET "EM_D<11>" LOC = "A19" ; -NET "EM_D<10>" LOC = "A17" ; -NET "EM_D<9>" LOC = "E15" ; -NET "EM_D<8>" LOC = "F15" ; -NET "EM_D<7>" LOC = "E16" ; -NET "EM_D<6>" LOC = "F16" ; -NET "EM_D<5>" LOC = "B17" ; -NET "EM_D<4>" LOC = "C17" ; -NET "EM_D<3>" LOC = "B19" ; -NET "EM_D<2>" LOC = "D19" ; -NET "EM_D<1>" LOC = "C19" ; -NET "EM_D<0>" LOC = "A20" ; - -NET "EM_A<10>" LOC = "C14" ; -NET "EM_A<9>" LOC = "C10" ; -NET "EM_A<8>" LOC = "C5" ; -NET "EM_A<7>" LOC = "A18" ; -NET "EM_A<6>" LOC = "A15" ; -NET "EM_A<5>" LOC = "A12" ; -NET "EM_A<4>" LOC = "A10" ; -NET "EM_A<3>" LOC = "E7" ; -NET "EM_A<2>" LOC = "A7" ; -NET "EM_A<1>" LOC = "C15" ; - -NET "EM_NCS6" LOC = "E17" ; -NET "EM_NCS5" LOC = "E10" ; -NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; - -NET "EM_CLK" LOC = "F11" ; -NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE<1>" LOC = "D14" ; -#NET "EM_NBE<0>" LOC = "A13" ; -NET "EM_NWE" LOC = "B13" ; -NET "EM_NOE" LOC = "A14" ; -NET "EM_NADV_ALE" LOC = "B15" ; -#NET "EM_NWP" LOC = "F13" ; -NET "overo_gpio64" LOC = "A4" ; # nRESET -NET "overo_gpio176" LOC = "B4" ; # IRQ - -## Debug pins -NET "debug_led<3>" LOC = "Y15" ; -NET "debug_led<2>" LOC = "K16" ; -NET "debug_led<1>" LOC = "J17" ; -NET "debug_led<0>" LOC = "H22" ; -NET "debug<0>" LOC = "G22" ; -NET "debug<1>" LOC = "H17" ; -NET "debug<2>" LOC = "H18" ; -NET "debug<3>" LOC = "K20" ; -NET "debug<4>" LOC = "J20" ; -NET "debug<5>" LOC = "K19" ; -NET "debug<6>" LOC = "K18" ; -NET "debug<7>" LOC = "L22" ; -NET "debug<8>" LOC = "K22" ; -NET "debug<9>" LOC = "N22" ; -NET "debug<10>" LOC = "M22" ; -NET "debug<11>" LOC = "N20" ; -NET "debug<12>" LOC = "N19" ; -NET "debug<13>" LOC = "R22" ; -NET "debug<14>" LOC = "P22" ; -NET "debug<15>" LOC = "N17" ; -NET "debug<16>" LOC = "P16" ; -NET "debug<17>" LOC = "U22" ; -NET "debug<18>" LOC = "P19" ; -NET "debug<19>" LOC = "R18" ; -NET "debug<20>" LOC = "U20" ; -NET "debug<21>" LOC = "T20" ; -NET "debug<22>" LOC = "R19" ; -NET "debug<23>" LOC = "R20" ; -NET "debug<24>" LOC = "W22" ; -NET "debug<25>" LOC = "Y22" ; -NET "debug<26>" LOC = "T18" ; -NET "debug<27>" LOC = "T17" ; -NET "debug<28>" LOC = "W19" ; -NET "debug<29>" LOC = "V20" ; -NET "debug<30>" LOC = "Y21" ; -NET "debug<31>" LOC = "AA22" ; -NET "debug_clk<0>" LOC = "N18" ; -NET "debug_clk<1>" LOC = "M17" ; - -NET "debug_pb" LOC = "C22" ; diff --git a/usrp2/top/u1e_ethdebug/u1e.v b/usrp2/top/u1e_ethdebug/u1e.v deleted file mode 100644 index 2a543a313..000000000 --- a/usrp2/top/u1e_ethdebug/u1e.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -//`define DCM 1 - -module u1e - (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input debug_pb, - - // GPMC - input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, - input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, - input EM_NADV_ALE, - - input overo_gpio64, input overo_gpio176 - ); - - assign debug_clk = {EM_CLK, EM_NADV_ALE}; - - assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb}; - - assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, - { EM_A[10], EM_A[7:1] }, - { EM_D[15:8] }, - { EM_D[7:0] } }; - - -endmodule // u1e -- cgit v1.2.3