From c1ddc5c082c053eaa46c8bc87064d3e3e56b0d9e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 16:29:44 -0800 Subject: copied over from safe_u1e --- usrp2/top/u1e/u1e.v | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 usrp2/top/u1e/u1e.v (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v new file mode 100644 index 000000000..e28a6a582 --- /dev/null +++ b/usrp2/top/u1e/u1e.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1e + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, + input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE + ); + + // FPGA-specific pins connections + wire clk_fpga; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + // Debug circuitry + reg [31:0] ctr; + always @(posedge clk_fpga) + ctr <= ctr + 1; + + + assign debug_led = ctr[27:25]; + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + + wire EM_output_enable = (~EM_NOE & ~EM_NCS4); + wire [15:0] EM_D_out; + + assign EM_D = EM_output_enable ? EM_D_out : 16'bz; + + ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port + (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out), + .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + + +endmodule // u2plus -- cgit v1.2.3 From b115e4d7661d64c6d20f0421908622b56a91e950 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 18:47:22 -0800 Subject: first cut at gpmc <-> wb bridge, split u1e into core, top, and tb --- .gitignore | 1 + usrp2/gpmc/gpmc.v | 66 ++++++++++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/Makefile | 3 ++- usrp2/top/u1e/tb_u1e.v | 25 ++++++++++++++++++ usrp2/top/u1e/u1e.ucf | 14 +++++----- usrp2/top/u1e/u1e.v | 33 ++++++------------------ usrp2/top/u1e/u1e_core.v | 52 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 160 insertions(+), 34 deletions(-) create mode 100644 .gitignore create mode 100644 usrp2/gpmc/gpmc.v create mode 100644 usrp2/top/u1e/tb_u1e.v create mode 100644 usrp2/top/u1e/u1e_core.v (limited to 'usrp2/top/u1e/u1e.v') diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..b25c15b81 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +*~ diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v new file mode 100644 index 000000000..96ee139fd --- /dev/null +++ b/usrp2/gpmc/gpmc.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module gpmc + (input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + input wb_clk, input wb_rst, + output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_ram; + reg [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; + + // CS4 is RAM_2PORT for high-speed data + ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port + (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), + .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + + // CS6 is Control, Wishbone bus bridge (wb master) + // Sync version + reg [1:0] cs_del, we_del, oe_del; + + // Synchronize the async control signals + always @(posedge wb_clk) + begin + cs_del <= { cs_del[0], EM_NCS6 }; + we_del <= { we_del[0], EM_NWE }; + oe_del <= { oe_del[0], EM_NOE }; + end + + always @(posedge wb_clk) + if(cs_del == 2'b10) // Falling Edge + wb_adr_o <= { EM_A, 1'b0 }; + + always @(posedge wb_clk) + if(we_del == 2'b10) // Falling Edge + begin + wb_dat_mosi <= EM_D; + wb_sel_o <= ~EM_NBE; + end + + always @(posedge wb_clk) + if(wb_ack_i) + EM_D_wb <= wb_dat_miso; + + // stb, oe_del, we_del + assign wb_cyc_o = wb_stb_o; + + always @(posedge wb_clk) + if( ~cs_del[0] & (we_del == 2'b10) ) + wb_we_o <= 1; + else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... + wb_we_o <= 0; + + always @(posedge wb_clk) + if( ~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10))) + wb_stb_o <= 1; + else if(wb_ack_i) + wb_stb_o <= 0; + +endmodule // gpmc diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index e9c101226..cdbdf995e 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -174,7 +174,8 @@ timing/time_receiver.v \ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ -top/u2_core/u2_core.v \ +gpmc/gpmc.v \ +top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ top/u1e/u1e.v diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v new file mode 100644 index 000000000..6e0c60e17 --- /dev/null +++ b/usrp2/top/u1e/tb_u1e.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module tb_u1e(); + + wire [2:0] debug_led; + wire [31:0] debug; + wire [1:0] debug_clk; + + + // GPMC + wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; + wire [15:0] EM_D; + wire [10:1] EM_A; + wire [1:0] EM_NBE; + + reg clk_fpga = 0; + always #100 clk_fpga = ~clk_fpga; + + u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + +endmodule // u1e diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index cb6d6372e..3b524a6ea 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -3,8 +3,6 @@ NET "CLK_FPGA_P" LOC = "Y11" ; NET "CLK_FPGA_N" LOC = "Y10" ; ## GPMC -NET "EM_CLK" LOC = "F11" ; - NET "EM_D<15>" LOC = "D13" ; NET "EM_D<14>" LOC = "D15" ; NET "EM_D<13>" LOC = "C16" ; @@ -33,20 +31,20 @@ NET "EM_A<3>" LOC = "E7" ; NET "EM_A<2>" LOC = "A7" ; NET "EM_A<1>" LOC = "C15" ; -#NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS6" LOC = "E17" ; #NET "EM_NCS5" LOC = "E10" ; NET "EM_NCS4" LOC = "E6" ; #NET "EM_NCS1" LOC = "D18" ; #NET "EM_NCS0" LOC = "D17" ; +NET "EM_CLK" LOC = "F11" ; NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE1" LOC = "D14" ; -#NET "EM_NBE0" LOC = "A13" ; -NET "EM_NWP" LOC = "F13" ; +NET "EM_NBE<1>" LOC = "D14" ; +NET "EM_NBE<0>" LOC = "A13" ; NET "EM_NWE" LOC = "B13" ; NET "EM_NOE" LOC = "A14" ; -NET "EM_NADV_ALE" LOC = "B15" ; - +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; ## Overo GPIO #NET "overo_gpio0" LOC = "F9" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index e28a6a582..8832d6e11 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -2,13 +2,12 @@ ////////////////////////////////////////////////////////////////////////////////// module u1e - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, // GPMC - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, - input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE ); // FPGA-specific pins connections @@ -17,25 +16,9 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - // Debug circuitry - reg [31:0] ctr; - always @(posedge clk_fpga) - ctr <= ctr + 1; - - - assign debug_led = ctr[27:25]; - assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, - { EM_D } }; - - wire EM_output_enable = (~EM_NOE & ~EM_NCS4); - wire [15:0] EM_D_out; - - assign EM_D = EM_output_enable ? EM_D_out : 16'bz; - - ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port - (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out), - .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - -endmodule // u2plus +endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v new file mode 100644 index 000000000..2481549b2 --- /dev/null +++ b/usrp2/top/u1e/u1e_core.v @@ -0,0 +1,52 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1e_core + (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE + ); + + // Debug circuitry + reg [31:0] ctr; + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign debug_led = ctr[27:25]; + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + + wire wb_clk, wb_rst; + wire wb_cyc, wb_stb, wb_we, wb_ack; + wire [1:0] wb_sel; + wire [10:0] wb_adr; + wire [15:0] wb_dat_mosi, wb_dat_miso; + + gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), .wb_we_o(wb_we), + .wb_ack_i(wb_ack)); + + assign wb_clk = clk_fpga; + reg [15:0] reg_fast, reg_slow; + + localparam [10:0] WB_ADR_REG_FAST = 36; + localparam [10:0] WB_ADR_REG_SLOW = 38; + + always @(posedge wb_clk) + if(wb_cyc & wb_stb & wb_we & (wb_adr == WB_ADR_REG_FAST)) + reg_fast <= wb_dat_mosi; + + assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx; + + assign wb_ack = wb_stb & wb_cyc; + + +endmodule // u2plus -- cgit v1.2.3 From f3c61700fbeba30f420ef939a1cabdc42bd15fb7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 18:05:42 -0800 Subject: Added I2C, UART, debug pins, misc wishbone stuff --- usrp2/top/u1e/u1e.ucf | 38 +++++----- usrp2/top/u1e/u1e.v | 12 ++- usrp2/top/u1e/u1e_core.v | 185 ++++++++++++++++++++++++++++++++++++++++------- 3 files changed, 187 insertions(+), 48 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 3b524a6ea..40d458034 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -56,10 +56,10 @@ NET "EM_NOE" LOC = "A14" ; #NET "overo_gpio65" LOC = "F8" ; #NET "overo_gpio127" LOC = "C8" ; #NET "overo_gpio128" LOC = "G8" ; -#NET "overo_gpio144" LOC = "A5" ; -#NET "overo_gpio145" LOC = "C7" ; -#NET "overo_gpio146" LOC = "A6" ; -#NET "overo_gpio147" LOC = "B6" ; +NET "overo_gpio144" LOC = "A5" ; # tx_have_space +NET "overo_gpio145" LOC = "C7" ; # tx_underrun +NET "overo_gpio146" LOC = "A6" ; # rx_have_data +NET "overo_gpio147" LOC = "B6" ; # rx_overrun #NET "overo_gpio163" LOC = "D7" ; #NET "overo_gpio170" LOC = "E8" ; #NET "overo_gpio176" LOC = "B4" ; @@ -68,13 +68,13 @@ NET "EM_NOE" LOC = "A14" ; #NET "overo_txd1" LOC = "C6" ; #NET "overo_rxd1" LOC = "D6" ; -#NET "FPGA_TXD" LOC = "U1" ; -#NET "FPGA_RXD" LOC = "T6" ; +NET "FPGA_TXD" LOC = "U1" ; +NET "FPGA_RXD" LOC = "T6" ; #NET "SYSEN" LOC = "C11" ; -#NET "db_scl" LOC = "U4" ; -#NET "db_sda" LOC = "U5" ; +NET "db_scl" LOC = "U4" ; +NET "db_sda" LOC = "U5" ; #NET "db_sclk_rx" LOC = "W3" ; #NET "db_miso_rx" LOC = "W2" ; #NET "db_mosi_rx" LOC = "V4" ; @@ -134,18 +134,18 @@ NET "debug<31>" LOC = "G3" ; NET "debug_clk<0>" LOC = "L6" ; NET "debug_clk<1>" LOC = "M5" ; -#NET "debug_pb<2>" LOC = "Y2" ; -#NET "debug_pb<1>" LOC = "AA1" ; -#NET "debug_pb<0>" LOC = "N3" ; +NET "debug_pb<2>" LOC = "Y2" ; +NET "debug_pb<1>" LOC = "AA1" ; +NET "debug_pb<0>" LOC = "N3" ; -#NET "dip_sw<7>" LOC = "T3" ; -#NET "dip_sw<6>" LOC = "U3" ; -#NET "dip_sw<5>" LOC = "M3" ; -#NET "dip_sw<4>" LOC = "N4" ; -#NET "dip_sw<3>" LOC = "J3" ; -#NET "dip_sw<2>" LOC = "J4" ; -#NET "dip_sw<1>" LOC = "J6" ; -#NET "dip_sw<0>" LOC = "J7" ; +NET "dip_sw<7>" LOC = "T3" ; +NET "dip_sw<6>" LOC = "U3" ; +NET "dip_sw<5>" LOC = "M3" ; +NET "dip_sw<4>" LOC = "N4" ; +NET "dip_sw<3>" LOC = "J3" ; +NET "dip_sw<2>" LOC = "J4" ; +NET "dip_sw<1>" LOC = "J6" ; +NET "dip_sw<0>" LOC = "J7" ; ## AD9862 Interface #NET "aux_sdi_codec" LOC = "F19" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 8832d6e11..4ca9b5580 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -4,10 +4,14 @@ module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input [2:0] debug_pb, input [7:0] dip_sw, output FPGA_TXD, input FPGA_RXD, // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, // I2C + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147 // Fifo controls ); // FPGA-specific pins connections @@ -17,8 +21,12 @@ module u1e clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .db_sda(db_sda), .db_scl(db_scl), + .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), + .rx_have_data(overo_gpio_146), .rx_overrun(overo_gpio147) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index b0edbb9b6..cad697858 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -3,49 +3,180 @@ module u1e_core (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - + input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd, + // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE - ); - - // Debug circuitry - reg [31:0] ctr=0; - always @(posedge clk_fpga) - ctr <= ctr + 1; + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, - assign debug_led = ctr[27:25]; - assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, - { EM_D } }; + inout db_sda, inout db_scl, + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun + ); wire wb_clk, wb_rst; - wire wb_cyc, wb_stb, wb_we, wb_ack; - wire [1:0] wb_sel; - wire [10:0] wb_adr; - wire [15:0] wb_dat_mosi, wb_dat_miso; + + assign tx_have_space = 0; + assign tx_underrun = 0; + assign rx_have_data = 0; + assign rx_overrun = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPMC Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), - .wb_sel_o(wb_sel), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), .wb_we_o(wb_we), - .wb_ack_i(wb_ack)); + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack)); assign wb_clk = clk_fpga; - reg [15:0] reg_fast, reg_slow; - localparam [10:0] WB_ADR_REG_FAST = 11'd36; - localparam [10:0] WB_ADR_REG_SLOW = 38; + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hF), .s9_addr(4'h9), .s9_mask(4'hF), + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s4_ack = 0; assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; + assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, LEDs and Switches + + reg [15:0] reg_fast, reg_slow; + localparam REG_FAST = 7'd4; + localparam REG_SWITCHES = 7'd5; always @(posedge wb_clk) - if(wb_cyc & wb_stb & wb_we & (wb_adr == WB_ADR_REG_FAST)) - reg_fast <= wb_dat_mosi; + if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_FAST)) + reg_fast <= s0_dat_mosi; - assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx; + assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : + (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + 16'hBEEF; + assign s0_ack = s0_stb & s0_cyc; - assign wb_ack = wb_stb & wb_cyc; - + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[4:2]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + /* + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + */ + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + // Debug circuitry + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board + endmodule // u1e_core -- cgit v1.2.3 From bc3c1fb34afba5fb4358f1b7eaaf3832360cc375 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 19:13:10 -0800 Subject: added gpio control to the wishbone --- usrp2/top/u1e/u1e.v | 2 +- usrp2/top/u1e/u1e_core.v | 23 +++++++++++++---------- 2 files changed, 14 insertions(+), 11 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 4ca9b5580..326476b21 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -27,6 +27,6 @@ module u1e .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), - .rx_have_data(overo_gpio_146), .rx_overrun(overo_gpio147) ); + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index cad697858..257156d4b 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -12,20 +12,15 @@ module u1e_core inout db_sda, inout db_scl, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun ); - - wire wb_clk, wb_rst; - - assign tx_have_space = 0; - assign tx_underrun = 0; - assign rx_have_data = 0; - assign rx_overrun = 0; + + wire wb_clk, wb_rst; // ///////////////////////////////////////////////////////////////////////////////////// // GPMC Slave to Wishbone Master localparam dw = 16; localparam aw = 11; localparam sw = 2; - + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; wire [aw-1:0] m0_adr; wire [sw-1:0] m0_sel; @@ -114,19 +109,27 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, LEDs and Switches - reg [15:0] reg_fast, reg_slow; + reg [15:0] reg_fast, reg_slow; localparam REG_FAST = 7'd4; - localparam REG_SWITCHES = 7'd5; + localparam REG_SWITCHES = 7'd6; + localparam REG_GPIOS = 7'd8; + + reg [3:0] reg_gpios; always @(posedge wb_clk) if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_FAST)) reg_fast <= s0_dat_mosi; + always @(posedge wb_clk) + if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_GPIOS)) + reg_gpios <= s0_dat_mosi; + assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; + assign { rx_overrun, rx_have_data, tx_underrun, tx_have_space } = reg_gpios; // ///////////////////////////////////////////////////////////////////////////////////// // Slave 1, UART -- cgit v1.2.3 From 2e4d962021334109b268c9080e5a5903b99be217 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 12:30:22 -0800 Subject: GPIOs now on the wishbone interface --- usrp2/top/u1e/Makefile | 2 +- usrp2/top/u1e/u1e.ucf | 64 ++++++++++++++++++++++++------------------------ usrp2/top/u1e/u1e.v | 6 +++-- usrp2/top/u1e/u1e_core.v | 19 ++++++++++++-- 4 files changed, 54 insertions(+), 37 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index cdbdf995e..9381789a7 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -64,7 +64,7 @@ control_lib/gray_send.v \ control_lib/icache.v \ control_lib/mux4.v \ control_lib/mux8.v \ -control_lib/nsgpio.v \ +control_lib/nsgpio16LE.v \ control_lib/ram_2port.v \ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 40d458034..f237eb60c 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -203,39 +203,39 @@ NET "dip_sw<0>" LOC = "J7" ; #NET "PPS_IN" LOC = "M17" ; -#NET "io_tx<0>" LOC = "AB20" ; -#NET "io_tx<1>" LOC = "Y17" ; -#NET "io_tx<2>" LOC = "Y16" ; -#NET "io_tx<3>" LOC = "U16" ; -#NET "io_tx<4>" LOC = "V16" ; -#NET "io_tx<5>" LOC = "AB19" ; -#NET "io_tx<6>" LOC = "AA19" ; -#NET "io_tx<7>" LOC = "U14" ; -#NET "io_tx<8>" LOC = "U15" ; -#NET "io_tx<9>" LOC = "AB17" ; -#NET "io_tx<10>" LOC = "AB18" ; -#NET "io_tx<11>" LOC = "Y13" ; -#NET "io_tx<12>" LOC = "W14" ; -#NET "io_tx<13>" LOC = "U13" ; -#NET "io_tx<14>" LOC = "AA15" ; -#NET "io_tx<15>" LOC = "AB14" ; +NET "io_tx<0>" LOC = "AB20" ; +NET "io_tx<1>" LOC = "Y17" ; +NET "io_tx<2>" LOC = "Y16" ; +NET "io_tx<3>" LOC = "U16" ; +NET "io_tx<4>" LOC = "V16" ; +NET "io_tx<5>" LOC = "AB19" ; +NET "io_tx<6>" LOC = "AA19" ; +NET "io_tx<7>" LOC = "U14" ; +NET "io_tx<8>" LOC = "U15" ; +NET "io_tx<9>" LOC = "AB17" ; +NET "io_tx<10>" LOC = "AB18" ; +NET "io_tx<11>" LOC = "Y13" ; +NET "io_tx<12>" LOC = "W14" ; +NET "io_tx<13>" LOC = "U13" ; +NET "io_tx<14>" LOC = "AA15" ; +NET "io_tx<15>" LOC = "AB14" ; -#NET "io_rx<0>" LOC = "Y8" ; -#NET "io_rx<1>" LOC = "Y9" ; -#NET "io_rx<2>" LOC = "V7" ; -#NET "io_rx<3>" LOC = "U8" ; -#NET "io_rx<4>" LOC = "V10" ; -#NET "io_rx<5>" LOC = "U9" ; -#NET "io_rx<6>" LOC = "AB7" ; -#NET "io_rx<7>" LOC = "AA8" ; -#NET "io_rx<8>" LOC = "W8" ; -#NET "io_rx<9>" LOC = "V8" ; -#NET "io_rx<10>" LOC = "AB5" ; -#NET "io_rx<11>" LOC = "AB6" ; -#NET "io_rx<12>" LOC = "AB4" ; -#NET "io_rx<13>" LOC = "AA4" ; -#NET "io_rx<14>" LOC = "W5" ; -#NET "io_rx<15>" LOC = "Y4" ; +NET "io_rx<0>" LOC = "Y8" ; +NET "io_rx<1>" LOC = "Y9" ; +NET "io_rx<2>" LOC = "V7" ; +NET "io_rx<3>" LOC = "U8" ; +NET "io_rx<4>" LOC = "V10" ; +NET "io_rx<5>" LOC = "U9" ; +NET "io_rx<6>" LOC = "AB7" ; +NET "io_rx<7>" LOC = "AA8" ; +NET "io_rx<8>" LOC = "W8" ; +NET "io_rx<9>" LOC = "V8" ; +NET "io_rx<10>" LOC = "AB5" ; +NET "io_rx<11>" LOC = "AB6" ; +NET "io_rx<12>" LOC = "AB4" ; +NET "io_rx<13>" LOC = "AA4" ; +NET "io_rx<14>" LOC = "W5" ; +NET "io_rx<15>" LOC = "Y4" ; #NET "CLKOUT2_CODEC" LOC = "U12" ; #NET "CLKOUT1_CODEC" LOC = "V12" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 326476b21..667372434 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -11,7 +11,8 @@ module u1e input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, // I2C - output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147 // Fifo controls + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + inout [15:0] io_tx, inout [15:0] io_rx ); // FPGA-specific pins connections @@ -27,6 +28,7 @@ module u1e .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), - .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147) ); + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), + .io_tx(io_tx), .io_rx(io_rx) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 257156d4b..ad3234b56 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -10,7 +10,8 @@ module u1e_core input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, - output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, + inout [15:0] io_tx, inout [15:0] io_rx ); wire wb_clk, wb_rst; @@ -102,7 +103,7 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s4_ack = 0; assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; + assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; @@ -172,6 +173,20 @@ module u1e_core IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////////////////// // Debug Pins -- cgit v1.2.3 From 030f6a21539207c058b982ffade384ec7a937ec2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 16:50:09 -0800 Subject: First cut at passing data buffers around on GPMC bus --- usrp2/gpmc/dbsm.v | 88 +++++++++++++++++++++++++++++++++++++++++++++++ usrp2/gpmc/gpmc.v | 45 ++++++++++++++++++------ usrp2/models/gpmc_model.v | 23 ++++++++++--- usrp2/top/u1e/tb_u1e.v | 11 ++++-- usrp2/top/u1e/u1e.v | 3 +- usrp2/top/u1e/u1e_core.v | 20 +++++++---- 6 files changed, 165 insertions(+), 25 deletions(-) create mode 100644 usrp2/gpmc/dbsm.v (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v new file mode 100644 index 000000000..0f27be46a --- /dev/null +++ b/usrp2/gpmc/dbsm.v @@ -0,0 +1,88 @@ + +module bsm + (input clk, input reset, input clear, + input write_done, + input read_done, + output readable, + output writeable); + + reg state; + localparam ST_WRITEABLE = 0; + localparam ST_READABLE = 1; + + always @(posedge clk) + if(reset | clear) + state <= ST_WRITEABLE; + else + case(state) + ST_WRITEABLE : + if(write_done) + state <= ST_READABLE; + ST_READABLE : + if(read_done) + state <= ST_WRITEABLE; + endcase // case (state) + + assign readable = (state == ST_READABLE); + assign writeable = (state == ST_WRITEABLE); + +endmodule // bsm + +module dbsm + (input clk, input reset, input clear, + output reg read_sel, output read_ready, input read_done, + output reg write_sel, output write_ready, input write_done); + + localparam NUM_BUFS = 2; + + wire [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf; + + // Two of these buffer state machines + genvar i; + for(i=0;i Date: Thu, 25 Feb 2010 21:09:34 -0800 Subject: invert the pushbuttons since they are active low --- usrp2/top/u1e/u1e.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 066d02ca4..329d61aa9 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -21,9 +21,9 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(debug_pb[2]), + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), -- cgit v1.2.3 From b74388567c0ed3048e45158ac077e31def59fea1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Mar 2010 15:49:23 -0700 Subject: connected spi pins, but the spi core still needs to be redone for 16 bit interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs --- usrp2/top/u1e/u1e.ucf | 72 ++++++++++++++++++++++++++---------------------- usrp2/top/u1e/u1e.v | 16 +++++++++++ usrp2/top/u1e/u1e_core.v | 12 ++++---- 3 files changed, 60 insertions(+), 40 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index f237eb60c..27f507c6b 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -68,27 +68,43 @@ NET "overo_gpio147" LOC = "B6" ; # rx_overrun #NET "overo_txd1" LOC = "C6" ; #NET "overo_rxd1" LOC = "D6" ; +## FTDI UART to USB converter NET "FPGA_TXD" LOC = "U1" ; NET "FPGA_RXD" LOC = "T6" ; #NET "SYSEN" LOC = "C11" ; +## I2C NET "db_scl" LOC = "U4" ; NET "db_sda" LOC = "U5" ; -#NET "db_sclk_rx" LOC = "W3" ; -#NET "db_miso_rx" LOC = "W2" ; -#NET "db_mosi_rx" LOC = "V4" ; -#NET "db_sen_rx" LOC = "V3" ; -#NET "db_sclk_tx" LOC = "Y1" ; -#NET "db_miso_tx" LOC = "W1" ; -#NET "db_mosi_tx" LOC = "R3" ; -#NET "db_sen_tx" LOC = "T4" ; -## Clock Gen -#NET "cgen_miso" LOC = "U2" ; -#NET "cgen_mosi" LOC = "V1" ; -#NET "cgen_sclk" LOC = "R5" ; -#NET "cgen_sen_b" LOC = "T1" ; +## SPI +### DBoard SPI +NET "db_sclk_rx" LOC = "W3" ; +NET "db_miso_rx" LOC = "W2" ; +NET "db_mosi_rx" LOC = "V4" ; +NET "db_sen_rx" LOC = "V3" ; +NET "db_sclk_tx" LOC = "Y1" ; +NET "db_miso_tx" LOC = "W1" ; +NET "db_mosi_tx" LOC = "R3" ; +NET "db_sen_tx" LOC = "T4" ; + +### AD9862 SPI and aux SPI Interfaces +#NET "aux_sdi_codec" LOC = "F19" ; +#NET "aux_sdo_codec" LOC = "F18" ; +#NET "aux_sclk_codec" LOC = "D21" ; +NET "sen_codec" LOC = "D20" ; +NET "mosi_codec" LOC = "E19" ; +NET "miso_codec" LOC = "F21" ; +NET "sclk_codec" LOC = "E20" ; + +### Clock Gen SPI +NET "cgen_miso" LOC = "U2" ; +NET "cgen_mosi" LOC = "V1" ; +NET "cgen_sclk" LOC = "R5" ; +NET "cgen_sen_b" LOC = "T1" ; + +## Clock gen control #NET "cgen_st_status" LOC = "D4" ; #NET "cgen_st_ld" LOC = "D1" ; #NET "cgen_st_refmon" LOC = "E1" ; @@ -147,17 +163,8 @@ NET "dip_sw<2>" LOC = "J4" ; NET "dip_sw<1>" LOC = "J6" ; NET "dip_sw<0>" LOC = "J7" ; -## AD9862 Interface -#NET "aux_sdi_codec" LOC = "F19" ; -#NET "aux_sdo_codec" LOC = "F18" ; -#NET "aux_sclk_codec" LOC = "D21" ; -#NET "reset_codec" LOC = "D22" ; -#NET "sen_codec" LOC = "D20" ; -#NET "mosi_codec" LOC = "E19" ; -#NET "miso_codec" LOC = "F21" ; -#NET "sclk_codec" LOC = "E20" ; - #NET "RXSYNC" LOC = "F22" ; +#NET "reset_codec" LOC = "D22" ; #NET "DB<11>" LOC = "E22" ; #NET "DB<10>" LOC = "J19" ; @@ -248,13 +255,12 @@ NET "io_rx<15>" LOC = "Y4" ; #NET "fpga_cfg_init_b" LOC = "W15" ; ## Unnamed, need to figure out what they do -#NET "unnamed_net37" LOC = "B1" ; -#NET "unnamed_net36" LOC = "B22" ; -#NET "unnamed_net35" LOC = "D2" ; -#NET "unnamed_net34" LOC = "A21" ; -#NET "unnamed_net45" LOC = "F7" ; -#NET "unnamed_net44" LOC = "V6" ; -#NET "unnamed_net43" LOC = "AA3" ; -#NET "unnamed_net42" LOC = "AB3" ; - -#NET "GND" LOC = "V19" ; +#NET "unnamed_net37" LOC = "B1" ; # TMS +#NET "unnamed_net36" LOC = "B22" ; # TDO +#NET "unnamed_net35" LOC = "D2" ; # TDI +#NET "unnamed_net34" LOC = "A21" ; # TCK +#NET "unnamed_net45" LOC = "F7" ; # PUDC_B +#NET "unnamed_net44" LOC = "V6" ; # M2 +#NET "unnamed_net43" LOC = "AA3" ; # M1 +#NET "unnamed_net42" LOC = "AB3" ; # M0 +#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 329d61aa9..f1f491a97 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -11,6 +11,12 @@ module u1e input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, // I2C + + output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI + output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI + output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI + output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls inout [15:0] io_tx, inout [15:0] io_rx ); @@ -21,6 +27,15 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + // SPI pins + wire mosi, sclk, miso; + assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; + assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; + assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; + assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; + assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | + (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), @@ -28,6 +43,7 @@ module u1e .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), + .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx) ); diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 2645225a0..c74d385ee 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -9,6 +9,8 @@ module u1e_core input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, + output sclk, output [7:0] sen, output mosi, input miso, + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx ); @@ -187,14 +189,11 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 2, SPI - /* spi_top shared_spi (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - */ + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); // ///////////////////////////////////////////////////////////////////////// // Slave 3, I2C @@ -216,7 +215,7 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // GPIOs -- Slave #4 -/* + wire [31:0] atr_lines; wire [31:0] debug_gpio_0, debug_gpio_1; @@ -226,7 +225,7 @@ module u1e_core .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); -*/ + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 @@ -247,7 +246,6 @@ module u1e_core assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; - assign {io_tx,io_rx} = debug_gpmc; assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { debug_txd, debug_rxd }; -- cgit v1.2.3 From 7a3064b67172aea1be00d188bdd79185a7df2ecf Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 26 Mar 2010 11:30:13 -0700 Subject: connect 2 clock gen controls and 3 status pins to the wishbone so they can be read/controlled from SW --- usrp2/top/u1e/u1e.ucf | 10 +++++----- usrp2/top/u1e/u1e.v | 4 ++++ usrp2/top/u1e/u1e_core.v | 20 +++++++++++++++++--- 3 files changed, 26 insertions(+), 8 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 27f507c6b..c39759d0b 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -105,11 +105,11 @@ NET "cgen_sclk" LOC = "R5" ; NET "cgen_sen_b" LOC = "T1" ; ## Clock gen control -#NET "cgen_st_status" LOC = "D4" ; -#NET "cgen_st_ld" LOC = "D1" ; -#NET "cgen_st_refmon" LOC = "E1" ; -#NET "cgen_sync_b" LOC = "M1" ; -#NET "cgen_ref_sel" LOC = "J1" ; +NET "cgen_st_status" LOC = "D4" ; +NET "cgen_st_ld" LOC = "D1" ; +NET "cgen_st_refmon" LOC = "E1" ; +NET "cgen_sync_b" LOC = "M1" ; +NET "cgen_ref_sel" LOC = "J1" ; ## Debug pins NET "debug_led<2>" LOC = "T5" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index f1f491a97..ab270879c 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -16,6 +16,8 @@ module u1e output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls inout [15:0] io_tx, inout [15:0] io_rx @@ -44,6 +46,8 @@ module u1e .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx) ); diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index c74d385ee..4f0227dfd 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -10,7 +10,8 @@ module u1e_core inout db_sda, inout db_scl, output sclk, output [7:0] sen, output mosi, input miso, - + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx ); @@ -151,13 +152,15 @@ module u1e_core assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 0, LEDs and Switches + // Slave 0, Misc LEDs, Switches, controls reg [15:0] reg_fast, reg_slow; localparam REG_FAST = 7'd4; localparam REG_SWITCHES = 7'd6; localparam REG_GPIOS = 7'd8; - + localparam REG_CGEN_ST = 7'd9; + localparam REG_CGEN_CTRL = 7'd10; + reg [3:0] reg_gpios; always @(posedge wb_clk) @@ -168,8 +171,19 @@ module u1e_core if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_GPIOS)) reg_gpios <= s0_dat_mosi; + reg [1:0] reg_cgen_ctrls; + + always @(posedge wb_clk) + if(wb_rst) + reg_cgen_ctrls <= 2'b11; + else if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_CGEN_CTRL)) + reg_cgen_ctrls <= s0_dat_mosi; + + assign {cgen_sync_b, cgen_ref_sel} = reg_cgen_ctrls; + assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; -- cgit v1.2.3 From 23316f1ac73c917757a70980c3a9f251852ee426 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 21:27:03 -0700 Subject: added pps and time capability --- usrp2/top/u1e/u1e.ucf | 2 +- usrp2/top/u1e/u1e.v | 6 ++++-- usrp2/top/u1e/u1e_core.v | 18 ++++++++++++++++-- 3 files changed, 21 insertions(+), 5 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index c39759d0b..1c8dfc197 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -208,7 +208,7 @@ NET "dip_sw<0>" LOC = "J7" ; #NET "TXSYNC" LOC = "U18" ; #NET "TXBLANK" LOC = "U19" ; -#NET "PPS_IN" LOC = "M17" ; +NET "PPS_IN" LOC = "M17" ; NET "io_tx<0>" LOC = "AB20" ; NET "io_tx<1>" LOC = "Y17" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index ab270879c..b8f716d26 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -20,7 +20,8 @@ module u1e input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls - inout [15:0] io_tx, inout [15:0] io_rx + inout [15:0] io_tx, inout [15:0] io_rx, + input PPS_IN ); // FPGA-specific pins connections @@ -50,6 +51,7 @@ module u1e .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), - .io_tx(io_tx), .io_rx(io_rx) ); + .io_tx(io_tx), .io_rx(io_rx), + .pps_in(PPS_IN) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 30396de3a..9e65faeed 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -13,7 +13,9 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx + inout [15:0] io_tx, inout [15:0] io_rx, + + input pps_in ); wire wb_clk = clk_fpga; @@ -249,7 +251,19 @@ module u1e_core (.clk_i(wb_clk), .rst_i(wb_rst), .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(), .run_tx(), .master_time(0), .ctrl_lines(atr_lines)); + .run_rx(0), .run_tx(0), .ctrl_lines(atr_lines)); + + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + localparam SR_TIME64 = 0; + wire pps_int; + wire [63:0] vita_time; + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From ae4b885e3533a73f0781e2fdb892f5d505081240 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 24 Apr 2010 22:58:06 -0700 Subject: Pass previously unused GPIOs to debug pins to help debug interrupts --- usrp2/top/u1e/u1e.ucf | 24 ++++++++++++------------ usrp2/top/u1e/u1e.v | 7 +++++++ usrp2/top/u1e/u1e_core.v | 6 ++---- 3 files changed, 21 insertions(+), 16 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 1c8dfc197..9c42b00ac 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -47,22 +47,22 @@ NET "EM_NOE" LOC = "A14" ; #NET "EM_NWP" LOC = "F13" ; ## Overo GPIO -#NET "overo_gpio0" LOC = "F9" ; -#NET "overo_gpio14" LOC = "C4" ; -#NET "overo_gpio21" LOC = "D5" ; -#NET "overo_gpio22" LOC = "A3" ; -#NET "overo_gpio23" LOC = "B3" ; -#NET "overo_gpio64" LOC = "A4" ; -#NET "overo_gpio65" LOC = "F8" ; -#NET "overo_gpio127" LOC = "C8" ; -#NET "overo_gpio128" LOC = "G8" ; +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug +NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug +NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug NET "overo_gpio144" LOC = "A5" ; # tx_have_space NET "overo_gpio145" LOC = "C7" ; # tx_underrun NET "overo_gpio146" LOC = "A6" ; # rx_have_data NET "overo_gpio147" LOC = "B6" ; # rx_overrun -#NET "overo_gpio163" LOC = "D7" ; -#NET "overo_gpio170" LOC = "E8" ; -#NET "overo_gpio176" LOC = "B4" ; +NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug ## Overo UART #NET "overo_txd1" LOC = "C6" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index b8f716d26..2ed6b71c8 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -20,6 +20,10 @@ module u1e input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO + input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO + input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO + inout [15:0] io_tx, inout [15:0] io_rx, input PPS_IN ); @@ -52,6 +56,9 @@ module u1e .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx), + .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, + {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, + {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), .pps_in(PPS_IN) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 9e65faeed..e67b1b158 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -13,9 +13,7 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx, - - input pps_in + inout [15:0] io_tx, inout [15:0] io_rx, input [11:0] misc_gpio, input pps_in ); wire wb_clk = clk_fpga; @@ -273,6 +271,6 @@ module u1e_core { EM_D } }; assign debug_gpio_0 = { debug_gpmc }; - assign debug_gpio_1 = { debug_txd, debug_rxd }; + assign debug_gpio_1 = { misc_gpio }; endmodule // u1e_core -- cgit v1.2.3 From 2ddaba2d8bdcdda07b949f007d2555cf57c7c8d7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 4 May 2010 15:06:03 -0700 Subject: added DAC output pins, and a sine wave generator to test them --- usrp2/top/u1e/u1e.ucf | 32 ++++++++++++++++---------------- usrp2/top/u1e/u1e.v | 4 ++++ usrp2/top/u1e/u1e_core.v | 45 +++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 63 insertions(+), 18 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 055a1ef17..a73ebceb8 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -191,22 +191,22 @@ NET "dip_sw<0>" LOC = "J7" ; #NET "DA<1>" LOC = "P22" ; #NET "DA<0>" LOC = "N17" ; -#NET "TX<13>" LOC = "P19" ; -#NET "TX<12>" LOC = "R18" ; -#NET "TX<11>" LOC = "U20" ; -#NET "TX<10>" LOC = "T20" ; -#NET "TX<9>" LOC = "R19" ; -#NET "TX<8>" LOC = "R20" ; -#NET "TX<7>" LOC = "W22" ; -#NET "TX<6>" LOC = "Y22" ; -#NET "TX<5>" LOC = "T18" ; -#NET "TX<4>" LOC = "T17" ; -#NET "TX<3>" LOC = "W19" ; -#NET "TX<2>" LOC = "V20" ; -#NET "TX<1>" LOC = "Y21" ; -#NET "TX<0>" LOC = "AA22" ; -#NET "TXSYNC" LOC = "U18" ; -#NET "TXBLANK" LOC = "U19" ; +NET "TX<13>" LOC = "P19" ; +NET "TX<12>" LOC = "R18" ; +NET "TX<11>" LOC = "U20" ; +NET "TX<10>" LOC = "T20" ; +NET "TX<9>" LOC = "R19" ; +NET "TX<8>" LOC = "R20" ; +NET "TX<7>" LOC = "W22" ; +NET "TX<6>" LOC = "Y22" ; +NET "TX<5>" LOC = "T18" ; +NET "TX<4>" LOC = "T17" ; +NET "TX<3>" LOC = "W19" ; +NET "TX<2>" LOC = "V20" ; +NET "TX<1>" LOC = "Y21" ; +NET "TX<0>" LOC = "AA22" ; +NET "TXSYNC" LOC = "U18" ; +NET "TXBLANK" LOC = "U19" ; NET "PPS_IN" LOC = "M17" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 2ed6b71c8..35818e8c8 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -25,6 +25,9 @@ module u1e input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] TX, output TXSYNC, output TXBLANK, + input PPS_IN ); @@ -56,6 +59,7 @@ module u1e .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx), + .tx(TX), .txsync(TXSYNC), .txblank(TXBLANK), .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index d5a3ddf68..74ffc4657 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -13,7 +13,10 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx, input [11:0] misc_gpio, input pps_in + inout [15:0] io_tx, inout [15:0] io_rx, + output reg [13:0] tx, output reg txsync, output txblank, + + input [11:0] misc_gpio, input pps_in ); wire wb_clk = clk_fpga; @@ -213,7 +216,7 @@ module u1e_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - assign { rx_overrun, tx_underrun } = reg_test; + assign { rx_overrun, tx_underrun } = 0; // reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : @@ -309,6 +312,44 @@ module u1e_core time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + + // ///////////////////////////////////////////////////////////////////////// + // TX + + assign txblank = 0; + + wire [23:0] freq = {reg_test,8'd0}; + + reg [23:0] tx_q_hold; + wire [23:0] tx_i, tx_q; + + reg tx_stb; + always @(posedge wb_clk) + tx_stb <= ~tx_stb; + + always @(posedge wb_clk) + if(tx_stb) + tx <= tx_i[23:10]; + else + tx <= tx_q_hold[23:10]; + + always @(posedge wb_clk) + if(tx_stb) + tx_q_hold <= tx_q; + + always @(posedge wb_clk) + txsync <= ~tx_stb; // TX Sync low indicates first data item + // We invert here if we don't use inv_txsync in the 9862 + + reg [23:0] phase; + always @(posedge wb_clk) + if(tx_stb) + phase <= phase + freq; + + cordic_z24 #(.bitwidth(24)) tx_cordic + (.clock(wb_clk), .reset(wb_rst), .enable(1), + .xi(24'd15000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo()); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From e5bc7a493252753ad9ddf6799e986fa19841221a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 15:50:06 -0700 Subject: vita49 tx and rx added in, all sample rates now at main system clock rate. --- usrp2/top/u1e/Makefile | 5 ++ usrp2/top/u1e/u1e.ucf | 50 ++++++------ usrp2/top/u1e/u1e.v | 68 ++++++++++++++-- usrp2/top/u1e/u1e_core.v | 204 ++++++++++++++++++++++++++++++----------------- 4 files changed, 220 insertions(+), 107 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 0277ef4f2..7f5085275 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -189,6 +189,11 @@ gpmc/gpmc_to_fifo_async.v \ gpmc/fifo_to_gpmc_async.v \ gpmc/fifo_watcher.v \ gpmc/gpmc_wb.v \ +vrt/vita_rx_control.v \ +vrt/vita_rx_framer.v \ +vrt/vita_tx_control.v \ +vrt/vita_tx_deframer.v \ +timing/time_compare.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ top/u1e/timing.ucf \ diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 2caa46639..659a9dce5 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -163,33 +163,33 @@ NET "dip_sw<2>" LOC = "J4" ; NET "dip_sw<1>" LOC = "J6" ; NET "dip_sw<0>" LOC = "J7" ; -#NET "RXSYNC" LOC = "F22" ; #NET "reset_codec" LOC = "D22" ; -#NET "DB<11>" LOC = "E22" ; -#NET "DB<10>" LOC = "J19" ; -#NET "DB<9>" LOC = "H20" ; -#NET "DB<8>" LOC = "G19" ; -#NET "DB<7>" LOC = "F20" ; -#NET "DB<6>" LOC = "K16" ; -#NET "DB<5>" LOC = "J17" ; -#NET "DB<4>" LOC = "H22" ; -#NET "DB<3>" LOC = "G22" ; -#NET "DB<2>" LOC = "H17" ; -#NET "DB<1>" LOC = "H18" ; -#NET "DB<0>" LOC = "K20" ; -#NET "DA<11>" LOC = "J20" ; -#NET "DA<10>" LOC = "K19" ; -#NET "DA<9>" LOC = "K18" ; -#NET "DA<8>" LOC = "L22" ; -#NET "DA<7>" LOC = "K22" ; -#NET "DA<6>" LOC = "N22" ; -#NET "DA<5>" LOC = "M22" ; -#NET "DA<4>" LOC = "N20" ; -#NET "DA<3>" LOC = "N19" ; -#NET "DA<2>" LOC = "R22" ; -#NET "DA<1>" LOC = "P22" ; -#NET "DA<0>" LOC = "N17" ; +NET "RXSYNC" LOC = "F22" ; +NET "DB<11>" LOC = "E22" ; +NET "DB<10>" LOC = "J19" ; +NET "DB<9>" LOC = "H20" ; +NET "DB<8>" LOC = "G19" ; +NET "DB<7>" LOC = "F20" ; +NET "DB<6>" LOC = "K16" ; +NET "DB<5>" LOC = "J17" ; +NET "DB<4>" LOC = "H22" ; +NET "DB<3>" LOC = "G22" ; +NET "DB<2>" LOC = "H17" ; +NET "DB<1>" LOC = "H18" ; +NET "DB<0>" LOC = "K20" ; +NET "DA<11>" LOC = "J20" ; +NET "DA<10>" LOC = "K19" ; +NET "DA<9>" LOC = "K18" ; +NET "DA<8>" LOC = "L22" ; +NET "DA<7>" LOC = "K22" ; +NET "DA<6>" LOC = "N22" ; +NET "DA<5>" LOC = "M22" ; +NET "DA<4>" LOC = "N20" ; +NET "DA<3>" LOC = "N19" ; +NET "DA<2>" LOC = "R22" ; +NET "DA<1>" LOC = "P22" ; +NET "DA<0>" LOC = "N17" ; NET "TX<13>" LOC = "P19" ; NET "TX<12>" LOC = "R18" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 35818e8c8..3018ff100 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -26,18 +26,46 @@ module u1e inout [15:0] io_tx, inout [15:0] io_rx, - output [13:0] TX, output TXSYNC, output TXBLANK, - + output reg [13:0] TX, output reg TXSYNC, output TXBLANK, + input [11:0] DA, input [11:0] DB, input RXSYNC, + input PPS_IN ); - // FPGA-specific pins connections - wire clk_fpga; + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in, clk_2x, dcm_rst, dcm_locked; IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + DCM #(.CLK_FEEDBACK ( "1X" ), + .CLKDV_DIVIDE ( 2.0 ), + .CLKFX_DIVIDE ( 1 ), + .CLKFX_MULTIPLY ( 2 ), + .CLKIN_DIVIDE_BY_2 ( "FALSE" ), + .CLKIN_PERIOD ( 15.625 ), + .CLKOUT_PHASE_SHIFT ( "NONE" ), + .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ), + .DFS_FREQUENCY_MODE ( "LOW" ), + .DLL_FREQUENCY_MODE ( "LOW" ), + .DUTY_CYCLE_CORRECTION ( "TRUE" ), + .FACTORY_JF ( 16'h8080 ), + .PHASE_SHIFT ( 0 ), + .STARTUP_WAIT ( "FALSE" )) + clk_doubler (.CLKFB(clk_fpga), .CLKIN(clk_fpga_in), .RST(dcm_rst), + .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), + .CLKDV(), .CLKFX(), .CLKFX180(), + .CLK2X(clk_2x), .CLK2X180(), + .CLK0(clk_fpga), .CLK90(), .CLK180(), .CLK270(), + .LOCKED(dcm_locked), .STATUS()); + + //BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + //BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + - // SPI pins + // ///////////////////////////////////////////////////////////////////////// + // SPI wire mosi, sclk, miso; assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; @@ -45,7 +73,27 @@ module u1e assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + always @(posedge clk_2x) + if(clk_fpga) + begin + TX <= tx_i; + TXSYNC <= 0; // Low indicates first data item + end + else + begin + TX <= tx_q; + TXSYNC <= 1; + end + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), @@ -59,10 +107,16 @@ module u1e .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx), - .tx(TX), .txsync(TXSYNC), .txblank(TXBLANK), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(DA), .rx_q(DB), .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), .pps_in(PPS_IN) ); + + // ///////////////////////////////////////////////////////////////////////// + // Local Debug + // assign debug_clk = {clk_fpga, clk_2x }; + // assign debug = { TXSYNC, TXBLANK, TX }; endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index ee193ffb9..002b28f7a 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,7 +1,8 @@ //`define LOOPBACK 1 -`define TIMED 1 +//`define TIMED 1 +`define DSP 1 module u1e_core (input clk_fpga, input rst_fpga, @@ -18,14 +19,31 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx, - output reg [13:0] tx, output reg txsync, output txblank, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, input [11:0] misc_gpio, input pps_in ); - + + localparam TXFIFOSIZE = 11; + localparam RXFIFOSIZE = 11; + localparam SR_TIME64 = 0; + localparam SR_RX_DSP = 0; + localparam SR_RX_CTRL = 0; + localparam SR_TX_DSP = 0; + localparam SR_TX_CTRL = 0; + wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; + wire pps_int; + wire [63:0] vita_time; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + // ///////////////////////////////////////////////////////////////////////////////////// // GPMC Slave to Wishbone Master localparam dw = 16; @@ -47,33 +65,36 @@ module u1e_core wire bus_error; - gpmc_async gpmc (.arst(wb_rst), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), - .EM_NOE(EM_NOE), - - .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), - .bus_error(bus_error), .bus_reset(0), - - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), - .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), - .wb_ack_i(m0_ack), - - .fifo_clk(wb_clk), .fifo_rst(wb_rst), - .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), - .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - - .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), - .debug(debug_gpmc)); + gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpmc (.arst(wb_rst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), + .bus_error(bus_error), .bus_reset(0), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + + .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), + .debug(debug_gpmc)); + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; + wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; + `ifdef LOOPBACK fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - wire rx_sof = rx_data[32]; - wire rx_eof = rx_data[33]; `endif // LOOPBACK `ifdef TIMED @@ -93,9 +114,7 @@ module u1e_core .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); // RX side - wire rx_enable, rx_src_rdy_int, rx_dst_rdy_int; - wire rx_sof = rx_data[32]; - wire rx_eof = rx_data[33]; + wire rx_enable; packet_generator32 pktgen32 (.clk(wb_clk), .reset(wb_rst), .clear(clear), @@ -108,7 +127,90 @@ module u1e_core .underrun(), .overrun(rx_overrun)); `endif // `ifdef TIMED + +`ifdef DSP + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx1_data; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), + .debug_rx(vrc_debug)); + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), + .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vrf_debug) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [99:0] tx1_data; + wire tx1_src_rdy, tx1_dst_rdy; + wire [15:0] tx_i_int, tx_q_int; + wire [31:0] debug_vtc, debug_vtd, debug_vt; + + vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time),.underrun(underrun), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug(debug_vtc) ); + + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .debug(debug_tx_dsp) ); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + +`else // !`ifdef DSP + // Dummy DSP signal generator for test purposes + wire [23:0] tx_i_int, tx_q_int; + wire [23:0] freq = {reg_test,8'd0}; + reg [23:0] phase; + + always @(posedge wb_clk) + phase <= phase + freq; + cordic_z24 #(.bitwidth(24)) tx_cordic + (.clock(wb_clk), .reset(wb_rst), .enable(1), + .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo()); + + assign tx_i = tx_i_int[23:10]; + assign tx_q = tx_q_int[23:10]; +`endif // !`ifdef DSP + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, @@ -181,8 +283,6 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, Misc LEDs, Switches, controls - reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; - localparam REG_LEDS = 7'd0; // out localparam REG_SWITCHES = 7'd2; // in localparam REG_CGEN_CTRL = 7'd4; // out @@ -288,10 +388,6 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - // only have 32 regs, 32 bits each with current setup... settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), @@ -311,51 +407,9 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // VITA Timing - localparam SR_TIME64 = 0; - wire pps_int; - wire [63:0] vita_time; - time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); - - - // ///////////////////////////////////////////////////////////////////////// - // TX - - assign txblank = 0; - - wire [23:0] freq = {reg_test,8'd0}; - - reg [23:0] tx_q_hold; - wire [23:0] tx_i, tx_q; - - reg tx_stb; - always @(posedge wb_clk) - tx_stb <= ~tx_stb; - - always @(posedge wb_clk) - if(tx_stb) - tx <= tx_i[23:10]; - else - tx <= tx_q_hold[23:10]; - - always @(posedge wb_clk) - if(tx_stb) - tx_q_hold <= tx_q; - - always @(posedge wb_clk) - txsync <= ~tx_stb; // TX Sync low indicates first data item - // We invert here if we don't use inv_txsync in the 9862 - - reg [23:0] phase; - always @(posedge wb_clk) - if(tx_stb) - phase <= phase + freq; - - cordic_z24 #(.bitwidth(24)) tx_cordic - (.clock(wb_clk), .reset(wb_rst), .enable(1), - .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo()); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From 7a776f9fce357b298566d0a417a1417c4484723c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 18:23:09 -0700 Subject: use DDR regs instead of a 2nd clock --- usrp2/top/u1e/u1e.v | 54 +++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 8 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 3018ff100..523aae1b9 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -1,6 +1,8 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// +//`define DCM 1 + module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, @@ -26,7 +28,7 @@ module u1e inout [15:0] io_tx, inout [15:0] io_rx, - output reg [13:0] TX, output reg TXSYNC, output TXBLANK, + output [13:0] TX, output TXSYNC, output TXBLANK, input [11:0] DA, input [11:0] DB, input RXSYNC, input PPS_IN @@ -34,11 +36,13 @@ module u1e // ///////////////////////////////////////////////////////////////////////// // Clocking - wire clk_fpga, clk_fpga_in, clk_2x, dcm_rst, dcm_locked; + wire clk_fpga, clk_fpga_in; IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); +`ifdef DCM + wire clk_2x, dcm_rst, dcm_locked; DCM #(.CLK_FEEDBACK ( "1X" ), .CLKDV_DIVIDE ( 2.0 ), .CLKFX_DIVIDE ( 1 ), @@ -59,11 +63,10 @@ module u1e .CLK2X(clk_2x), .CLK2X180(), .CLK0(clk_fpga), .CLK90(), .CLK180(), .CLK270(), .LOCKED(dcm_locked), .STATUS()); - - //BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - //BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - +`else // !`ifdef DCM + BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); +`endif // !`ifdef DCM + // ///////////////////////////////////////////////////////////////////////// // SPI wire mosi, sclk, miso; @@ -79,6 +82,10 @@ module u1e assign TXBLANK = 0; wire [13:0] tx_i, tx_q; + +`ifdef DCM + reg [13:0] TX; + reg TXSYNC; always @(posedge clk_2x) if(clk_fpga) @@ -91,7 +98,38 @@ module u1e TX <= tx_q; TXSYNC <= 1; end - +`else // !`ifdef DCM + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(tx_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + +`endif // !`ifdef DCM + // ///////////////////////////////////////////////////////////////////////// // Main U1E Core u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), -- cgit v1.2.3 From 1d9d3dcc7b460e25881d182e74429f91cef31a50 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 17 Aug 2010 15:50:27 -0700 Subject: delay the q channel to make the channels line up on the AD9862 --- usrp2/top/u1e/u1e.v | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 523aae1b9..9536b5ced 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -99,6 +99,11 @@ module u1e TXSYNC <= 1; end `else // !`ifdef DCM + + reg[13:0] delay_q; + always @(posedge clk_fpga) + delay_q <= tx_q; + genvar i; generate for(i=0;i<14;i=i+1) @@ -111,7 +116,7 @@ module u1e .C1(~clk_fpga), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(tx_i[i]), // 1-bit data input (associated with C0) - .D1(tx_q[i]), // 1-bit data input (associated with C1) + .D1(delay_q[i]), // 1-bit data input (associated with C1) .R(1'b0), // 1-bit reset input .S(1'b0)); // 1-bit set input end // block: gen_dacout -- cgit v1.2.3 From 08eb9d2937c28edfb6d1fe7fb168ef77727406d5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 9 Sep 2010 14:19:14 -0700 Subject: updated pins to match rev2, removed dip switch, etc. seems to compile ok. --- usrp2/top/u1e/u1e.ucf | 251 +++++++++++++++++++++++------------------------ usrp2/top/u1e/u1e.v | 8 +- usrp2/top/u1e/u1e_core.v | 8 +- 3 files changed, 130 insertions(+), 137 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 659a9dce5..51968d24a 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -54,8 +54,10 @@ NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug, also used on the passthru image as the cgen_sen_b pin -NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug + +NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 +NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 + NET "overo_gpio144" LOC = "A5" ; # tx_have_space NET "overo_gpio145" LOC = "C7" ; # tx_underrun NET "overo_gpio146" LOC = "A6" ; # rx_have_data @@ -69,146 +71,137 @@ NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug #NET "overo_rxd1" LOC = "D6" ; ## FTDI UART to USB converter -NET "FPGA_TXD" LOC = "U1" ; -NET "FPGA_RXD" LOC = "T6" ; +NET "FPGA_TXD" LOC = "G19" ; +NET "FPGA_RXD" LOC = "F20" ; #NET "SYSEN" LOC = "C11" ; ## I2C -NET "db_scl" LOC = "U4" ; -NET "db_sda" LOC = "U5" ; +NET "db_scl" LOC = "F19" ; +NET "db_sda" LOC = "F18" ; ## SPI ### DBoard SPI -NET "db_sclk_rx" LOC = "W3" ; -NET "db_miso_rx" LOC = "W2" ; -NET "db_mosi_rx" LOC = "V4" ; -NET "db_sen_rx" LOC = "V3" ; -NET "db_sclk_tx" LOC = "Y1" ; -NET "db_miso_tx" LOC = "W1" ; -NET "db_mosi_tx" LOC = "R3" ; -NET "db_sen_tx" LOC = "T4" ; +NET "db_sclk_rx" LOC = "D21" ; +NET "db_miso_rx" LOC = "D22" ; +NET "db_mosi_rx" LOC = "D20" ; +NET "db_sen_rx" LOC = "E19" ; +NET "db_sclk_tx" LOC = "F21" ; +NET "db_miso_tx" LOC = "E20" ; +NET "db_mosi_tx" LOC = "G17" ; +NET "db_sen_tx" LOC = "G18" ; ### AD9862 SPI and aux SPI Interfaces -#NET "aux_sdi_codec" LOC = "F19" ; -#NET "aux_sdo_codec" LOC = "F18" ; -#NET "aux_sclk_codec" LOC = "D21" ; -NET "sen_codec" LOC = "D20" ; -NET "mosi_codec" LOC = "E19" ; -NET "miso_codec" LOC = "F21" ; -NET "sclk_codec" LOC = "E20" ; +#NET "aux_sdi_codec" LOC = "G3" ; +#NET "aux_sdo_codec" LOC = "F3" ; +#NET "aux_sclk_codec" LOC = "C1" ; +NET "sen_codec" LOC = "F5" ; +NET "mosi_codec" LOC = "F4" ; +NET "miso_codec" LOC = "H4" ; +NET "sclk_codec" LOC = "H3" ; ### Clock Gen SPI -NET "cgen_miso" LOC = "U2" ; -NET "cgen_mosi" LOC = "V1" ; -NET "cgen_sclk" LOC = "R5" ; -NET "cgen_sen_b" LOC = "T1" ; +NET "cgen_miso" LOC = "F22" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; ## Clock gen control -NET "cgen_st_status" LOC = "D4" ; -NET "cgen_st_ld" LOC = "D1" ; -NET "cgen_st_refmon" LOC = "E1" ; -NET "cgen_sync_b" LOC = "M1" ; -NET "cgen_ref_sel" LOC = "J1" ; +NET "cgen_st_status" LOC = "P20" ; +NET "cgen_st_ld" LOC = "R17" ; +NET "cgen_st_refmon" LOC = "P17" ; +NET "cgen_sync_b" LOC = "U18" ; +NET "cgen_ref_sel" LOC = "U19" ; ## Debug pins -NET "debug_led<2>" LOC = "T5" ; -NET "debug_led<1>" LOC = "R2" ; -NET "debug_led<0>" LOC = "R1" ; -NET "debug<0>" LOC = "P6" ; -NET "debug<1>" LOC = "R6" ; -NET "debug<2>" LOC = "P1" ; -NET "debug<3>" LOC = "P2" ; -NET "debug<4>" LOC = "N6" ; -NET "debug<5>" LOC = "N5" ; -NET "debug<6>" LOC = "N1" ; -NET "debug<7>" LOC = "K2" ; -NET "debug<8>" LOC = "K3" ; -NET "debug<9>" LOC = "K6" ; -NET "debug<10>" LOC = "L5" ; -NET "debug<11>" LOC = "H2" ; -NET "debug<12>" LOC = "K4" ; -NET "debug<13>" LOC = "K5" ; -NET "debug<14>" LOC = "G1" ; -NET "debug<15>" LOC = "H1" ; -NET "debug<16>" LOC = "H5" ; -NET "debug<17>" LOC = "H6" ; -NET "debug<18>" LOC = "E3" ; -NET "debug<19>" LOC = "E4" ; -NET "debug<20>" LOC = "G5" ; -NET "debug<21>" LOC = "G6" ; -NET "debug<22>" LOC = "F2" ; -NET "debug<23>" LOC = "F1" ; -NET "debug<24>" LOC = "H3" ; -NET "debug<25>" LOC = "H4" ; -NET "debug<26>" LOC = "F4" ; -NET "debug<27>" LOC = "F5" ; -NET "debug<28>" LOC = "C2" ; -NET "debug<29>" LOC = "C1" ; -NET "debug<30>" LOC = "F3" ; -NET "debug<31>" LOC = "G3" ; -NET "debug_clk<0>" LOC = "L6" ; -NET "debug_clk<1>" LOC = "M5" ; +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; -NET "debug_pb<2>" LOC = "Y2" ; -NET "debug_pb<1>" LOC = "AA1" ; -NET "debug_pb<0>" LOC = "N3" ; +NET "debug_pb" LOC = "C22" ; -NET "dip_sw<7>" LOC = "T3" ; -NET "dip_sw<6>" LOC = "U3" ; -NET "dip_sw<5>" LOC = "M3" ; -NET "dip_sw<4>" LOC = "N4" ; -NET "dip_sw<3>" LOC = "J3" ; -NET "dip_sw<2>" LOC = "J4" ; -NET "dip_sw<1>" LOC = "J6" ; -NET "dip_sw<0>" LOC = "J7" ; +#NET "reset_codec" LOC = "C2" ; -#NET "reset_codec" LOC = "D22" ; +NET "RXSYNC" LOC = "F2" ; +NET "DB<11>" LOC = "G6" ; +NET "DB<10>" LOC = "G5" ; +NET "DB<9>" LOC = "E4" ; +NET "DB<8>" LOC = "E3" ; +NET "DB<7>" LOC = "H6" ; +NET "DB<6>" LOC = "H5" ; +NET "DB<5>" LOC = "H1" ; +NET "DB<4>" LOC = "G1" ; +NET "DB<3>" LOC = "K5" ; +NET "DB<2>" LOC = "K4" ; +NET "DB<1>" LOC = "H2" ; +NET "DB<0>" LOC = "L5" ; -NET "RXSYNC" LOC = "F22" ; -NET "DB<11>" LOC = "E22" ; -NET "DB<10>" LOC = "J19" ; -NET "DB<9>" LOC = "H20" ; -NET "DB<8>" LOC = "G19" ; -NET "DB<7>" LOC = "F20" ; -NET "DB<6>" LOC = "K16" ; -NET "DB<5>" LOC = "J17" ; -NET "DB<4>" LOC = "H22" ; -NET "DB<3>" LOC = "G22" ; -NET "DB<2>" LOC = "H17" ; -NET "DB<1>" LOC = "H18" ; -NET "DB<0>" LOC = "K20" ; -NET "DA<11>" LOC = "J20" ; -NET "DA<10>" LOC = "K19" ; -NET "DA<9>" LOC = "K18" ; -NET "DA<8>" LOC = "L22" ; -NET "DA<7>" LOC = "K22" ; -NET "DA<6>" LOC = "N22" ; -NET "DA<5>" LOC = "M22" ; -NET "DA<4>" LOC = "N20" ; -NET "DA<3>" LOC = "N19" ; -NET "DA<2>" LOC = "R22" ; -NET "DA<1>" LOC = "P22" ; -NET "DA<0>" LOC = "N17" ; +NET "DA<11>" LOC = "K6" ; +NET "DA<10>" LOC = "K3" ; +NET "DA<9>" LOC = "K2" ; +NET "DA<8>" LOC = "N1" ; +NET "DA<7>" LOC = "N5" ; +NET "DA<6>" LOC = "N6" ; +NET "DA<5>" LOC = "P2" ; +NET "DA<4>" LOC = "P1" ; +NET "DA<3>" LOC = "R6" ; +NET "DA<2>" LOC = "P6" ; +NET "DA<1>" LOC = "R1" ; +NET "DA<0>" LOC = "R2" ; -NET "TX<13>" LOC = "P19" ; -NET "TX<12>" LOC = "R18" ; -NET "TX<11>" LOC = "U20" ; -NET "TX<10>" LOC = "T20" ; -NET "TX<9>" LOC = "R19" ; -NET "TX<8>" LOC = "R20" ; -NET "TX<7>" LOC = "W22" ; -NET "TX<6>" LOC = "Y22" ; -NET "TX<5>" LOC = "T18" ; -NET "TX<4>" LOC = "T17" ; -NET "TX<3>" LOC = "W19" ; -NET "TX<2>" LOC = "V20" ; -NET "TX<1>" LOC = "Y21" ; -NET "TX<0>" LOC = "AA22" ; -NET "TXSYNC" LOC = "U18" ; -NET "TXBLANK" LOC = "U19" ; +NET "TX<13>" LOC = "T6" ; +NET "TX<12>" LOC = "U1" ; +NET "TX<11>" LOC = "T1" ; +NET "TX<10>" LOC = "R5" ; +NET "TX<9>" LOC = "V1" ; +NET "TX<8>" LOC = "U2" ; +NET "TX<7>" LOC = "T4" ; +NET "TX<6>" LOC = "R3" ; +NET "TX<5>" LOC = "W1" ; +NET "TX<4>" LOC = "Y1" ; +NET "TX<3>" LOC = "V3" ; +NET "TX<2>" LOC = "V4" ; +NET "TX<1>" LOC = "W2" ; +NET "TX<0>" LOC = "W3" ; +NET "TXSYNC" LOC = "U5" ; +NET "TXBLANK" LOC = "U4" ; -NET "PPS_IN" LOC = "M17" ; +NET "PPS_IN" LOC = "M5" ; NET "io_tx<0>" LOC = "AB20" ; NET "io_tx<1>" LOC = "Y17" ; @@ -255,12 +248,12 @@ NET "io_rx<15>" LOC = "Y4" ; #NET "fpga_cfg_init_b" LOC = "W15" ; ## Unused -#NET "unnamed_net37" LOC = "B1" ; # TMS -#NET "unnamed_net36" LOC = "B22" ; # TDO -#NET "unnamed_net35" LOC = "D2" ; # TDI -#NET "unnamed_net34" LOC = "A21" ; # TCK -#NET "unnamed_net45" LOC = "F7" ; # PUDC_B -#NET "unnamed_net44" LOC = "V6" ; # M2 -#NET "unnamed_net43" LOC = "AA3" ; # M1 -#NET "unnamed_net42" LOC = "AB3" ; # M0 +#NET "unnamed_net53" LOC = "B1" ; # TMS +#NET "unnamed_net52" LOC = "B22" ; # TDO +#NET "unnamed_net51" LOC = "D2" ; # TDI +#NET "unnamed_net50" LOC = "A21" ; # TCK +#NET "unnamed_net59" LOC = "F7" ; # PUDC_B +#NET "unnamed_net58" LOC = "V6" ; # M2 +#NET "unnamed_net57" LOC = "AA3" ; # M1 +#NET "unnamed_net56" LOC = "AB3" ; # M0 #NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 9536b5ced..7ddbfd537 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -5,8 +5,8 @@ module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input [2:0] debug_pb, input [7:0] dip_sw, output FPGA_TXD, input FPGA_RXD, + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, output FPGA_TXD, input FPGA_RXD, // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -137,9 +137,9 @@ module u1e // ///////////////////////////////////////////////////////////////////////// // Main U1E Core - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 5c4b6de6c..42333a722 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -6,8 +6,8 @@ module u1e_core (input clk_fpga, input rst_fpga, - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd, + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -343,11 +343,11 @@ module u1e_core assign rx_enable = xfer_rate[14]; assign rate = xfer_rate[7:0]; - assign { debug_led[2],debug_led[0],debug_led[1] } = {run_rx,run_tx,reg_leds[0]}; // LEDs are arranged funny on board + assign { debug_led[3:0] } = {run_rx,run_tx,reg_leds[1:0]}; assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : - (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } : (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : -- cgit v1.2.3 From d78fd935865e3ebece9163a85b4b8043beef4eee Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 21 Sep 2010 17:00:44 -0700 Subject: fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift --- usrp2/top/u1e/u1e.ucf | 38 +++++++++++++++++++------------------- usrp2/top/u1e/u1e.v | 37 ++++++------------------------------- 2 files changed, 25 insertions(+), 50 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 51968d24a..5581b1dbd 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -95,10 +95,10 @@ NET "db_sen_tx" LOC = "G18" ; #NET "aux_sdi_codec" LOC = "G3" ; #NET "aux_sdo_codec" LOC = "F3" ; #NET "aux_sclk_codec" LOC = "C1" ; -NET "sen_codec" LOC = "F5" ; -NET "mosi_codec" LOC = "F4" ; +NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; +NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; NET "miso_codec" LOC = "H4" ; -NET "sclk_codec" LOC = "H3" ; +NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; ### Clock Gen SPI NET "cgen_miso" LOC = "F22" ; @@ -184,22 +184,22 @@ NET "DA<2>" LOC = "P6" ; NET "DA<1>" LOC = "R1" ; NET "DA<0>" LOC = "R2" ; -NET "TX<13>" LOC = "T6" ; -NET "TX<12>" LOC = "U1" ; -NET "TX<11>" LOC = "T1" ; -NET "TX<10>" LOC = "R5" ; -NET "TX<9>" LOC = "V1" ; -NET "TX<8>" LOC = "U2" ; -NET "TX<7>" LOC = "T4" ; -NET "TX<6>" LOC = "R3" ; -NET "TX<5>" LOC = "W1" ; -NET "TX<4>" LOC = "Y1" ; -NET "TX<3>" LOC = "V3" ; -NET "TX<2>" LOC = "V4" ; -NET "TX<1>" LOC = "W2" ; -NET "TX<0>" LOC = "W3" ; -NET "TXSYNC" LOC = "U5" ; -NET "TXBLANK" LOC = "U4" ; +NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; NET "PPS_IN" LOC = "M5" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 7ddbfd537..ee087e59d 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -1,8 +1,6 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -//`define DCM 1 - module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, @@ -41,11 +39,10 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); -`ifdef DCM - wire clk_2x, dcm_rst, dcm_locked; + wire clk_2x, dcm_rst, dcm_locked, clk_fb; DCM #(.CLK_FEEDBACK ( "1X" ), - .CLKDV_DIVIDE ( 2.0 ), - .CLKFX_DIVIDE ( 1 ), + .CLKDV_DIVIDE ( 2 ), + .CLKFX_DIVIDE ( 2 ), .CLKFX_MULTIPLY ( 2 ), .CLKIN_DIVIDE_BY_2 ( "FALSE" ), .CLKIN_PERIOD ( 15.625 ), @@ -57,15 +54,12 @@ module u1e .FACTORY_JF ( 16'h8080 ), .PHASE_SHIFT ( 0 ), .STARTUP_WAIT ( "FALSE" )) - clk_doubler (.CLKFB(clk_fpga), .CLKIN(clk_fpga_in), .RST(dcm_rst), + clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), .CLKDV(), .CLKFX(), .CLKFX180(), - .CLK2X(clk_2x), .CLK2X180(), - .CLK0(clk_fpga), .CLK90(), .CLK180(), .CLK270(), + .CLK2X(), .CLK2X180(), + .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), .LOCKED(dcm_locked), .STATUS()); -`else // !`ifdef DCM - BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); -`endif // !`ifdef DCM // ///////////////////////////////////////////////////////////////////////// // SPI @@ -83,23 +77,6 @@ module u1e assign TXBLANK = 0; wire [13:0] tx_i, tx_q; -`ifdef DCM - reg [13:0] TX; - reg TXSYNC; - - always @(posedge clk_2x) - if(clk_fpga) - begin - TX <= tx_i; - TXSYNC <= 0; // Low indicates first data item - end - else - begin - TX <= tx_q; - TXSYNC <= 1; - end -`else // !`ifdef DCM - reg[13:0] delay_q; always @(posedge clk_fpga) delay_q <= tx_q; @@ -133,8 +110,6 @@ module u1e .R(1'b0), // 1-bit reset input .S(1'b0)); // 1-bit set input -`endif // !`ifdef DCM - // ///////////////////////////////////////////////////////////////////////// // Main U1E Core u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), -- cgit v1.2.3 From 27eb894c397f758528f59bc24f2ac645f0fccc4b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 23 Sep 2010 11:40:19 -0700 Subject: watch the ethernet chip select on our debug bus --- usrp2/top/u1e/u1e.ucf | 2 +- usrp2/top/u1e/u1e.v | 7 ++++--- usrp2/top/u1e/u1e_core.v | 5 +++-- 3 files changed, 8 insertions(+), 6 deletions(-) (limited to 'usrp2/top/u1e/u1e.v') diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 5581b1dbd..0c487a601 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -32,7 +32,7 @@ NET "EM_A<2>" LOC = "A7" ; NET "EM_A<1>" LOC = "C15" ; NET "EM_NCS6" LOC = "E17" ; -#NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS5" LOC = "E10" ; NET "EM_NCS4" LOC = "E6" ; #NET "EM_NCS1" LOC = "D18" ; #NET "EM_NCS0" LOC = "D17" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index ee087e59d..445b14a03 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -8,7 +8,8 @@ module u1e // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, // I2C @@ -116,8 +117,8 @@ module u1e .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), + .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 42333a722..619e44b8a 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -11,7 +11,8 @@ module u1e_core // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, output sclk, output [7:0] sen, output mosi, input miso, @@ -439,7 +440,7 @@ module u1e_core assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; -- cgit v1.2.3