From b115e4d7661d64c6d20f0421908622b56a91e950 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 16 Feb 2010 18:47:22 -0800
Subject: first cut at gpmc <-> wb bridge, split u1e into core, top, and tb

---
 usrp2/top/u1e/tb_u1e.v | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 usrp2/top/u1e/tb_u1e.v

(limited to 'usrp2/top/u1e/tb_u1e.v')

diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
new file mode 100644
index 000000000..6e0c60e17
--- /dev/null
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -0,0 +1,25 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module tb_u1e();
+   
+   wire [2:0] debug_led;
+   wire [31:0] debug;
+   wire [1:0] debug_clk;
+   
+   
+   // GPMC
+   wire       EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
+   wire [15:0] EM_D;
+   wire [10:1] EM_A;
+   wire [1:0]  EM_NBE;
+   
+   reg  clk_fpga = 0;
+   always #100 clk_fpga = ~clk_fpga;
+   
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
+		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+   
+endmodule // u1e
-- 
cgit v1.2.3


From d4649caee02a1c76802dc4f8d7d76bb31b14ce09 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 16 Feb 2010 22:49:02 -0800
Subject: wishbone bridge now with minimal functionality.  Need to check timing
 and handle wait states.

---
 usrp2/gpmc/gpmc.v         |  4 +--
 usrp2/models/gpmc_model.v | 70 +++++++++++++++++++++++++++++++++++++++++++++++
 usrp2/top/u1e/.gitignore  |  2 ++
 usrp2/top/u1e/README      |  4 +++
 usrp2/top/u1e/cmdfile     | 19 +++++++++++++
 usrp2/top/u1e/make.sim    |  7 +++++
 usrp2/top/u1e/tb_u1e.v    | 17 +++++++++---
 usrp2/top/u1e/u1e_core.v  |  9 +++---
 8 files changed, 121 insertions(+), 11 deletions(-)
 create mode 100644 usrp2/models/gpmc_model.v
 create mode 100644 usrp2/top/u1e/README
 create mode 100644 usrp2/top/u1e/cmdfile
 create mode 100644 usrp2/top/u1e/make.sim

(limited to 'usrp2/top/u1e/tb_u1e.v')

diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
index 96ee139fd..1963af6e6 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc.v
@@ -18,8 +18,8 @@ module gpmc
 
    // CS4 is RAM_2PORT for high-speed data
    ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port
-     (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram),
-      .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob());
+     (.clka(wb_clk), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram),
+      .clkb(wb_clk), .enb(0), .web(0), .addrb(0), .dib(0), .dob());
 
    // CS6 is Control, Wishbone bus bridge (wb master)
    // Sync version
diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
new file mode 100644
index 000000000..ce3acaacf
--- /dev/null
+++ b/usrp2/models/gpmc_model.v
@@ -0,0 +1,70 @@
+
+
+module gpmc_model
+  (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   assign EM_CLK = 0;
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+   
+   initial
+     begin
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 #2;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #4;
+	 EM_NCS6 <= 0;
+	 #5;
+	 EM_NWE <= 0;
+	 #41;
+	 EM_NWE <= 1;
+	 EM_NCS6 <= 1;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input [10:0] addr;
+      begin
+	 #2;
+	 EM_A <= addr[10:1];
+	 #4;
+	 EM_NCS6 <= 0;
+	 #5;
+	 EM_NOE <= 0;
+	 #41;
+	 EM_NOE <= 1;
+	 EM_NCS6 <= 1;
+	 EM_A <= 10'bz;
+	 $display("Data Read from GPMC: %X",EM_D);
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000;
+	GPMC_Write(36,16'hBEEF);
+	#1000;
+	GPMC_Read(36);
+	#1000;
+	$finish;
+     end
+   
+endmodule // gpmc_model
diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore
index f8b57ea21..8d872713e 100644
--- a/usrp2/top/u1e/.gitignore
+++ b/usrp2/top/u1e/.gitignore
@@ -2,3 +2,5 @@
 build
 *.log
 *.cmd
+tb_u1e
+*.lxt
diff --git a/usrp2/top/u1e/README b/usrp2/top/u1e/README
new file mode 100644
index 000000000..14c7a4955
--- /dev/null
+++ b/usrp2/top/u1e/README
@@ -0,0 +1,4 @@
+
+make clean
+make sim
+./tb_u1e -lxt2
diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile
new file mode 100644
index 000000000..5e4db5c65
--- /dev/null
+++ b/usrp2/top/u1e/cmdfile
@@ -0,0 +1,19 @@
+
+# My stuff
+-y .
+-y ../../control_lib
+-y ../../control_lib/newfifo
+-y ../../sdr_lib
+-y ../../timing
+-y ../../coregen
+-y ../../gpmc
+
+# Models
+-y ../../models
+
+# Open Cores
+-y ../opencores/spi/rtl/verilog
++incdir+../opencores/spi/rtl/verilog
+-y ../opencores/i2c/rtl/verilog
++incdir+../opencores/i2c/rtl/verilog
+
diff --git a/usrp2/top/u1e/make.sim b/usrp2/top/u1e/make.sim
new file mode 100644
index 000000000..1c163884c
--- /dev/null
+++ b/usrp2/top/u1e/make.sim
@@ -0,0 +1,7 @@
+all: sim
+
+sim:	
+	iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e
+
+clean:
+	rm -f tb_u1e *.vcd *.lxt a.out
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 6e0c60e17..85d2b49f0 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -6,8 +6,12 @@ module tb_u1e();
    wire [2:0] debug_led;
    wire [31:0] debug;
    wire [1:0] debug_clk;
-   
-   
+
+   initial begin
+      $dumpfile("tb_u1e.lxt");
+      $dumpvars(0,tb_u1e);
+   end
+    
    // GPMC
    wire       EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
    wire [15:0] EM_D;
@@ -15,11 +19,16 @@ module tb_u1e();
    wire [1:0]  EM_NBE;
    
    reg  clk_fpga = 0;
-   always #100 clk_fpga = ~clk_fpga;
+   always #15.625 clk_fpga = ~clk_fpga;
    
    u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
 		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+   gpmc_model gpmc_model
+     (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
+      .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
    
-endmodule // u1e
+endmodule // tb_u1e
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 2481549b2..b0edbb9b6 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -10,7 +10,7 @@ module u1e_core
    );
 
    // Debug circuitry
-   reg [31:0] 	ctr;
+   reg [31:0] 	ctr=0;
    always @(posedge clk_fpga)
      ctr <= ctr + 1;
    
@@ -37,7 +37,7 @@ module u1e_core
    assign wb_clk = clk_fpga;
    reg [15:0] 	reg_fast, reg_slow;
 
-   localparam [10:0] WB_ADR_REG_FAST = 36;
+   localparam [10:0] WB_ADR_REG_FAST = 11'd36;
    localparam [10:0] WB_ADR_REG_SLOW = 38;
    
    always @(posedge wb_clk)
@@ -47,6 +47,5 @@ module u1e_core
    assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx;
 
    assign wb_ack = wb_stb & wb_cyc;
-   
-   
-endmodule // u2plus
+      
+endmodule // u1e_core
-- 
cgit v1.2.3


From e56b4767451dcdca41512faba634b812e44d2e1d Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 18 Feb 2010 18:03:26 -0800
Subject: Fixed paths to help icarus find opencores and xilinx models.  Added
 Xilinx global set and reset module.

---
 usrp2/top/u1e/cmdfile  | 9 +++++----
 usrp2/top/u1e/tb_u1e.v | 2 ++
 2 files changed, 7 insertions(+), 4 deletions(-)

(limited to 'usrp2/top/u1e/tb_u1e.v')

diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile
index 5e4db5c65..291c723b8 100644
--- a/usrp2/top/u1e/cmdfile
+++ b/usrp2/top/u1e/cmdfile
@@ -10,10 +10,11 @@
 
 # Models
 -y ../../models
+-y /opt/Xilinx/10.1/ISE/verilog/src/unisims
 
 # Open Cores
--y ../opencores/spi/rtl/verilog
-+incdir+../opencores/spi/rtl/verilog
--y ../opencores/i2c/rtl/verilog
-+incdir+../opencores/i2c/rtl/verilog
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
 
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 85d2b49f0..319645af6 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -7,6 +7,8 @@ module tb_u1e();
    wire [31:0] debug;
    wire [1:0] debug_clk;
 
+   xlnx_glbl glbl (.GSR(),.GTS());
+
    initial begin
       $dumpfile("tb_u1e.lxt");
       $dumpvars(0,tb_u1e);
-- 
cgit v1.2.3


From 030f6a21539207c058b982ffade384ec7a937ec2 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 25 Feb 2010 16:50:09 -0800
Subject: First cut at passing data buffers around on GPMC bus

---
 usrp2/gpmc/dbsm.v         | 88 +++++++++++++++++++++++++++++++++++++++++++++++
 usrp2/gpmc/gpmc.v         | 45 ++++++++++++++++++------
 usrp2/models/gpmc_model.v | 23 ++++++++++---
 usrp2/top/u1e/tb_u1e.v    | 11 ++++--
 usrp2/top/u1e/u1e.v       |  3 +-
 usrp2/top/u1e/u1e_core.v  | 20 +++++++----
 6 files changed, 165 insertions(+), 25 deletions(-)
 create mode 100644 usrp2/gpmc/dbsm.v

(limited to 'usrp2/top/u1e/tb_u1e.v')

diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v
new file mode 100644
index 000000000..0f27be46a
--- /dev/null
+++ b/usrp2/gpmc/dbsm.v
@@ -0,0 +1,88 @@
+
+module bsm
+  (input clk, input reset, input clear,
+   input write_done,
+   input read_done,
+   output readable,
+   output writeable);
+
+   reg 	  state;
+   localparam ST_WRITEABLE = 0;
+   localparam ST_READABLE = 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= ST_WRITEABLE;
+     else
+       case(state)
+	 ST_WRITEABLE :
+	   if(write_done)
+	     state <= ST_READABLE;
+	 ST_READABLE :
+	   if(read_done)
+	     state <= ST_WRITEABLE;
+       endcase // case (state)
+
+   assign readable = (state == ST_READABLE);
+   assign writeable = (state == ST_WRITEABLE);
+   
+endmodule // bsm
+
+module dbsm
+  (input clk, input reset, input clear,
+   output reg read_sel, output read_ready, input read_done,
+   output reg write_sel, output write_ready, input write_done);
+
+   localparam NUM_BUFS = 2;
+
+   wire       [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf;
+   
+   // Two of these buffer state machines
+   genvar     i;
+   for(i=0;i<NUM_BUFS;i=i+1)
+     generate
+	bsm bsm(.clk(clk), .reset(reset), .clear(clear), 
+		.write_done((write_sel == i) & write_done), 
+		.read_done((read_sel == i) & read_done), 
+		.readable(readable[i]), .writeable(writeable[i]));
+     endgenerate
+   
+   reg 	 full;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  write_sel <= 0;
+	  full <= 0;
+       end
+     else
+       if(write_done)
+	 if(writeable[write_sel]==(NUM_BUFS-1))
+	   begin
+	      write_sel <= 0;
+	      if(read_sel == 0)
+		full <= 1;
+	   end
+	 else
+	   begin
+	      write_sel <= write_sel + 1;
+	      if(read_sel == write_sel + 1)
+		full <= 1;
+	   end // else: !if(writeable[write_sel]==(NUM_BUFS-1))
+       else if(read_done)
+	 full <= 0;
+
+   always @(posedge clk)
+     if(reset | clear)
+       read_sel <= 0;
+     else
+       if(read_done)
+	 if(readable[read_sel]==(NUM_BUFS-1))
+	   read_sel <= 0;
+	 else
+	   read_sel <= read_sel + 1;
+          
+   assign write_ready = writeable[write_sel];
+   assign read_ready = readable[read_sel];
+
+endmodule // dbsm
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
index 88f6809f8..91d02bfec 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc.v
@@ -1,4 +1,3 @@
-`timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 
 module gpmc
@@ -6,6 +5,9 @@ module gpmc
    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
    input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
 
+   // GPIOs for FIFO signalling
+   output rx_have_data, output tx_have_space,
+   
    // Wishbone signals
    input wb_clk, input wb_rst,
    output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
@@ -13,8 +15,8 @@ module gpmc
 
    // RAM Interface signals
    input ram_clk, 
-   input read_en, input read_sel, input [8:0] read_addr, output [31:0] read_data, output read_rdy,
-   input write_en, input write_sel, input [8:0] write_addr, input [31:0] write_data, output write_rdy
+   input read_en, input [8:0] read_addr, output [31:0] read_data, output read_ready, input read_done,
+   input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done
    );
 
    wire 	EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
@@ -25,14 +27,35 @@ module gpmc
 
    // CS4 is RAM_2PORT for high-speed data
    // Writes go into one RAM, reads come from the other
+
+
+   // ////////////////////////////////////////////
+   // Write path
+   wire 	read_sel_in, write_sel_in, clear_in;
+   wire 	write_done_in = ~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF);
+   
+   ram_2port_mixed_width buffer_in
+     (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({write_sel_in,EM_A}), .di16(EM_D), .do16(),
+      .clk32(ram_clk), .en32(read_en), .we32(0), .addr32({read_sel_in,read_addr}), .di32(0), .do32(read_data));
+
+   dbsm dbsm_in(.clk(wb_clk), .reset(wb_rst), .clear(clear_in),
+		.read_sel(read_sel_in), .read_ready(read_ready), .read_done(read_done),
+		.write_sel(write_sel_in), .write_ready(tx_have_space), .write_done(write_done_in));
+
+   
+   
+   // ////////////////////////////////////////////
+   // Read path
+   wire 	read_sel_out, write_sel_out, clear_out;
+   wire 	read_done_out = ~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF);
    
-   ram_2port_mixed_width buffer_from_host
-     (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({store_pg,EM_A}), .di16(EM_D), .do16(),
-      .clk32(ram_clk), .en32(read_en), .we32(0), .addr32({read_sel,read_addr}), .di32(0), .do32(read_data));
+   ram_2port_mixed_width buffer_out
+     (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_out,EM_A}), .di16(0), .do16(EM_D_ram),
+      .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel_out,write_addr}), .di32(write_data), .do32());
 
-   ram_2port_mixed_width buffer_to_host
-     (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({retr_page,EM_A}), .di16(0), .do16(EM_D_ram),
-      .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel,write_addr}), .di32(write_data), .do32());
+   dbsm dbsm_out(.clk(wb_clk), .reset(wb_rst), .clear(clear_out),
+		 .read_sel(read_sel_out), .read_ready(rx_have_data), .read_done(read_done_out),
+		 .write_sel(write_sel_out), .write_ready(write_ready), .write_done(write_done));
 
    // CS6 is Control, Wishbone bus bridge (wb master)
    // Sync version
@@ -67,13 +90,13 @@ module gpmc
    assign wb_cyc_o = wb_stb_o;
 
    always @(posedge wb_clk)
-     if( ~cs_del[0] & (we_del == 2'b10) )
+     if(~cs_del[0] & (we_del == 2'b10) )
        wb_we_o <= 1;
      else if(wb_ack_i)  // Turn off we when done.  Could also use we_del[0], others...
        wb_we_o <= 0;
 
    always @(posedge wb_clk)
-     if( ~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))
+     if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))
        wb_stb_o <= 1;
      else if(wb_ack_i)
        wb_stb_o <= 0;
diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
index 38dde1fa5..1e7dcdde5 100644
--- a/usrp2/models/gpmc_model.v
+++ b/usrp2/models/gpmc_model.v
@@ -22,6 +22,7 @@ module gpmc_model
      end
    
    task GPMC_Write;
+      input ctrl;
       input [10:0] addr;
       input [15:0] data;
       begin
@@ -29,10 +30,14 @@ module gpmc_model
 	 EM_A <= addr[10:1];
 	 EM_D_int <= data;
 	 #2.01;
-	 EM_NCS6 <= 0;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
 	 #14;
 	 EM_NWE <= 0;
 	 #77.5;
+	 EM_NCS4 <= 1;
 	 EM_NCS6 <= 1;
 	 //#1.5;
 	 EM_NWE <= 1;
@@ -43,15 +48,20 @@ module gpmc_model
    endtask // GPMC_Write
 
    task GPMC_Read;
+      input ctrl;
       input [10:0] addr;
       begin
 	 #1.3;
 	 EM_A <= addr[10:1];
 	 #3;
-	 EM_NCS6 <= 0;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
 	 #14;
 	 EM_NOE <= 0;
 	 #77.5;
+	 EM_NCS4 <= 1;
 	 EM_NCS6 <= 1;
 	 //#1.5;
 	 $display("Data Read from GPMC: %X",EM_D);
@@ -64,9 +74,14 @@ module gpmc_model
    initial
      begin
 	#1000;
-	GPMC_Write(36,16'hBEEF);
+	GPMC_Write(1,36,16'hF00D);
 	#1000;
-	GPMC_Read(36);
+	GPMC_Read(1,36);
+	#1000;
+	GPMC_Write(0,36,16'hF00D);
+	GPMC_Write(0,38,16'hF00D);
+	GPMC_Write(0,40,16'hF00D);
+	GPMC_Write(0,11'h7FFE,16'hF00D);
 	#1000;
 	$finish;
      end
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 319645af6..3cae74c8a 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 1ps / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 
 module tb_u1e();
@@ -20,10 +20,15 @@ module tb_u1e();
    wire [10:1] EM_A;
    wire [1:0]  EM_NBE;
    
-   reg  clk_fpga = 0;
+   reg  clk_fpga = 0, rst_fpga = 1;
    always #15.625 clk_fpga = ~clk_fpga;
+
+   initial #200
+     @(posedge clk_fpga)
+       rst_fpga <= 0;
    
-   u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), 
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
 		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index 667372434..066d02ca4 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -21,7 +21,8 @@ module u1e
    IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
    clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
 
-   u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(debug_pb[2]),
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
 		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 12c566b6c..7feafeda8 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -1,8 +1,7 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
 
 module u1e_core
-  (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+  (input clk_fpga, input rst_fpga,
+   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
    input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd,
    
    // GPMC
@@ -14,7 +13,8 @@ module u1e_core
    inout [15:0] io_tx, inout [15:0] io_rx
    );
    
-   wire   wb_clk, wb_rst;
+   wire 	wb_clk = clk_fpga;
+   wire 	wb_rst = rst_fpga;
    
    // /////////////////////////////////////////////////////////////////////////////////////
    // GPMC Slave to Wishbone Master
@@ -31,10 +31,18 @@ module u1e_core
 	      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
 	      .EM_NOE(EM_NOE),
 
+	      .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
+	      
 	      .wb_clk(wb_clk), .wb_rst(wb_rst),
 	      .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
 	      .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
-	      .wb_ack_i(m0_ack));
+	      .wb_ack_i(m0_ack),
+
+	      .ram_clk(wb_clk),
+	      .read_en(read_en), .read_addr(read_addr), .read_data(read_data), 
+	      .read_ready(read_ready), .read_done(read_done),
+	      .write_en(write_en), .write_addr(write_addr), .write_data(write_data), 
+	      .write_ready(write_ready), .write_done(write_done) );
 
    assign wb_clk = clk_fpga;
 
@@ -130,7 +138,7 @@ module u1e_core
 			16'hBEEF;
    assign s0_ack = s0_stb & s0_cyc;
 
-   assign { rx_overrun, rx_have_data, tx_underrun, tx_have_space } = reg_gpios;
+   assign { rx_overrun, tx_underrun } = reg_gpios;
 
    // /////////////////////////////////////////////////////////////////////////////////////
    // Slave 1, UART
-- 
cgit v1.2.3


From d7342b46abac60bf4e2811ac4798dc4e06b5844f Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 15 Apr 2010 14:51:41 -0700
Subject: synchronous and asynchronous gpmc models

---
 usrp2/models/gpmc_model.v       | 95 ----------------------------------------
 usrp2/models/gpmc_model_async.v | 95 ++++++++++++++++++++++++++++++++++++++++
 usrp2/models/gpmc_model_sync.v  | 97 +++++++++++++++++++++++++++++++++++++++++
 usrp2/top/u1e/tb_u1e.v          |  2 +-
 4 files changed, 193 insertions(+), 96 deletions(-)
 delete mode 100644 usrp2/models/gpmc_model.v
 create mode 100644 usrp2/models/gpmc_model_async.v
 create mode 100644 usrp2/models/gpmc_model_sync.v

(limited to 'usrp2/top/u1e/tb_u1e.v')

diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
deleted file mode 100644
index 6066ede6e..000000000
--- a/usrp2/models/gpmc_model.v
+++ /dev/null
@@ -1,95 +0,0 @@
-
-
-module gpmc_model
-  (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
-   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
-   output reg EM_NWE, output reg EM_NOE );
-
-   assign EM_CLK = 0;
-   reg [15:0] EM_D_int;
-   assign EM_D = EM_D_int;
-   
-   initial
-     begin
-	EM_A <= 10'bz;
-	EM_NBE <= 2'b11;
-	EM_NWE <= 1;
-	EM_NOE <= 1;
-	EM_NCS4 <= 1;
-	EM_NCS6 <= 1;
-	EM_D_int <= 16'bz;
- 	EM_WAIT0 <= 0;  // FIXME this is actually an input
-     end
-   
-   task GPMC_Write;
-      input ctrl;
-      input [10:0] addr;
-      input [15:0] data;
-      begin
-	 #2.3;
-	 EM_A <= addr[10:1];
-	 EM_D_int <= data;
-	 #2.01;
-	 if(ctrl)
-	   EM_NCS6 <= 0;
-	 else
-	   EM_NCS4 <= 0;
-	 #14;
-	 EM_NWE <= 0;
-	 #77.5;
-	 EM_NCS4 <= 1;
-	 EM_NCS6 <= 1;
-	 //#1.5;
-	 EM_NWE <= 1;
-	 #60;
-	 EM_A <= 10'bz;
-	 EM_D_int <= 16'bz;
-      end
-   endtask // GPMC_Write
-
-   task GPMC_Read;
-      input ctrl;
-      input [10:0] addr;
-      begin
-	 #1.3;
-	 EM_A <= addr[10:1];
-	 #3;
-	 if(ctrl)
-	   EM_NCS6 <= 0;
-	 else
-	   EM_NCS4 <= 0;
-	 #14;
-	 EM_NOE <= 0;
-	 #77.5;
-	 EM_NCS4 <= 1;
-	 EM_NCS6 <= 1;
-	 //#1.5;
-	 $display("Data Read from GPMC: %X",EM_D);
-	 EM_NOE <= 1;
-	 #254;
-	 EM_A <= 10'bz;
-      end
-   endtask // GPMC_Read
-   
-   initial
-     begin
-	#1000;
-	GPMC_Write(1,36,16'hF00D);
-	#1000;
-	GPMC_Read(1,36);
-	#1000;
-	GPMC_Write(0,36,16'h1234);
-	GPMC_Write(0,38,16'h5678);
-	GPMC_Write(0,40,16'h9abc);
-	GPMC_Write(0,11'h2F4,16'hF00D);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	GPMC_Write(0,11'h7FE,16'hDEAD);
-	#100000;
-	$finish;
-     end
-   
-endmodule // gpmc_model
diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v
new file mode 100644
index 000000000..a63a5a8fd
--- /dev/null
+++ b/usrp2/models/gpmc_model_async.v
@@ -0,0 +1,95 @@
+
+
+module gpmc_model_async
+  (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   assign EM_CLK = 0;
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+   
+   initial
+     begin
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input ctrl;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 #2.3;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #2.01;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14;
+	 EM_NWE <= 0;
+	 #77.5;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 EM_NWE <= 1;
+	 #60;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input ctrl;
+      input [10:0] addr;
+      begin
+	 #1.3;
+	 EM_A <= addr[10:1];
+	 #3;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14;
+	 EM_NOE <= 0;
+	 #77.5;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 $display("Data Read from GPMC: %X",EM_D);
+	 EM_NOE <= 1;
+	 #254;
+	 EM_A <= 10'bz;
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000;
+	GPMC_Write(1,36,16'hF00D);
+	#1000;
+	GPMC_Read(1,36);
+	#1000;
+	GPMC_Write(0,36,16'h1234);
+	GPMC_Write(0,38,16'h5678);
+	GPMC_Write(0,40,16'h9abc);
+	GPMC_Write(0,11'h2F4,16'hF00D);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	#100000;
+	$finish;
+     end
+   
+endmodule // gpmc_model_async
diff --git a/usrp2/models/gpmc_model_sync.v b/usrp2/models/gpmc_model_sync.v
new file mode 100644
index 000000000..641720c15
--- /dev/null
+++ b/usrp2/models/gpmc_model_sync.v
@@ -0,0 +1,97 @@
+
+
+module gpmc_model_sync
+  (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+
+   initial
+     begin
+	EM_CLK <= 0;
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input ctrl;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 EM_CLK <= 1;
+	 #10;
+	 EM_CLK <= 0;
+	 EM_NWE <= 0;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #10;
+	 EM_CLK <= 1;
+	 #10;
+	 EM_CLK <= 0;
+	 EM_NWE <= 1;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+	 #100;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input ctrl;
+      input [10:0] addr;
+      begin
+	 #1.3;
+	 EM_A <= addr[10:1];
+	 #3;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14;
+	 EM_NOE <= 0;
+	 #77.5;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 $display("Data Read from GPMC: %X",EM_D);
+	 EM_NOE <= 1;
+	 #254;
+	 EM_A <= 10'bz;
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000;
+	GPMC_Write(1,36,16'hF00D);
+	#1000;
+	GPMC_Read(1,36);
+	#1000;
+	GPMC_Write(0,36,16'h1234);
+	GPMC_Write(0,38,16'h5678);
+	GPMC_Write(0,40,16'h9abc);
+	GPMC_Write(0,11'h2F4,16'hF00D);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	#100000;
+	$finish;
+     end
+   
+endmodule // gpmc_model
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 3cae74c8a..31e4fcb69 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -33,7 +33,7 @@ module tb_u1e();
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
 		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
 
-   gpmc_model gpmc_model
+   gpmc_model_async gpmc_model_async
      (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
       .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
       .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
-- 
cgit v1.2.3


From 449a420f4024004abc49f3a17d224910710def92 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 15 Apr 2010 16:16:31 -0700
Subject: async gpmc progress

---
 usrp2/gpmc/fifo_to_gpmc_async.v |  45 +++++++++++++++++
 usrp2/gpmc/gpmc_async.v         | 108 ++++++++++++++++++++++++++++++++++++++++
 usrp2/top/u1e/tb_u1e.v          |   4 +-
 usrp2/top/u1e/u1e_core.v        |  34 +++++++------
 4 files changed, 173 insertions(+), 18 deletions(-)
 create mode 100644 usrp2/gpmc/fifo_to_gpmc_async.v
 create mode 100644 usrp2/gpmc/gpmc_async.v

(limited to 'usrp2/top/u1e/tb_u1e.v')

diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v
new file mode 100644
index 000000000..4f253e1b5
--- /dev/null
+++ b/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -0,0 +1,45 @@
+
+// Assumes an asynchronous GPMC cycle
+//   If a packet bigger or smaller than we are told is sent, behavior is undefined.
+//   If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
+//   If there is a bus error, we should be reset
+
+module fifo_to_gpmc_async
+  (input clk, input reset, input clear,
+   input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [15:0] EM_D, input EM_NCS, input EM_NOE,
+   input [15:0] frame_len, output reg bus_error);
+
+   // Synchronize the async control signals
+   reg [1:0] 	cs_del, oe_del;
+   reg [15:0] 	counter;
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  cs_del <= 2'b11;
+	  oe_del <= 2'b11;
+       end
+     else
+       begin
+	  cs_del <= { cs_del[0], EM_NCS };
+	  oe_del <= { oe_del[0], EM_NOE };
+       end
+
+   //wire do_read = (~cs_del[0] & (oe_del == 2'b10));
+   wire do_read = (~cs_del[1] & (oe_del == 2'b01));  // change output on trailing edge
+   wire first_read = (counter == 0);
+   wire last_read = ((counter+1) == frame_len);
+
+   assign EM_D = data_i[15:0];
+
+   assign dst_rdy_o = do_read;
+
+   always @(posedge clk)
+     if(reset)
+       bus_error <= 0;
+     else if(dst_rdy_o & ~src_rdy_i)
+       bus_error <= 1;
+   
+
+endmodule // fifo_to_gpmc_async
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
new file mode 100644
index 000000000..c4cf0ef89
--- /dev/null
+++ b/usrp2/gpmc/gpmc_async.v
@@ -0,0 +1,108 @@
+//////////////////////////////////////////////////////////////////////////////////
+
+module gpmc_async
+  (// GPMC signals
+   input arst,
+   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+   
+   // GPIOs for FIFO signalling
+   output rx_have_data, output tx_have_space, output bus_error, input bus_reset,
+   
+   // Wishbone signals
+   input wb_clk, input wb_rst,
+   output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+   output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+
+   // FIFO interface
+   input fifo_clk, input fifo_rst,
+   output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
+   input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+
+   output [31:0] debug
+   );
+
+   wire 	EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+   wire [15:0] 	EM_D_fifo;
+   wire [15:0] 	EM_D_wb;
+
+   assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
+
+   wire 	bus_error_tx, bus_error_rx;
+   assign bus_error = bus_error_tx | bus_error_rx;
+   
+   // CS4 is RAM_2PORT for DATA PATH (high-speed data)
+   //    Writes go into one RAM, reads come from the other
+   // CS6 is for CONTROL PATH (wishbone)
+
+   // ////////////////////////////////////////////
+   // TX Data Path
+
+   wire [17:0] 	tx18_data, tx18b_data;
+   wire 	tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
+   wire [15:0] 	tx_fifo_space, tx_frame_len;
+   
+   assign tx_frame_len = 10;
+   
+   gpmc_to_fifo_async gpmc_to_fifo_async
+     (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
+      .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+      .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
+      .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
+      .bus_error(bus_error_tx) );
+   
+   fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
+      .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied());
+
+   fifo19_to_fifo36 f19_to_f36
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
+      .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i));
+   
+   // ////////////////////////////////////////////
+   // RX Data Path
+
+   wire [17:0] 	rx18_data, rx18b_data;
+   wire 	rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
+   wire [15:0] 	rx_fifo_space, rx_frame_len;
+   assign rx_frame_len = tx_frame_len;
+   
+   fifo36_to_fifo18 f18_to_f36
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o),
+      .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) );
+
+   fifo_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
+      .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied());
+
+   fifo_to_gpmc_async fifo_to_gpmc_async
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
+      .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
+      .frame_len(rx_frame_len), .bus_error(bus_error_rx) );
+
+   fifo_watcher fifo_watcher
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]),
+      .have_packet(), .length(), .next() );
+
+   assign rx_have_data = 0;
+   
+   // ////////////////////////////////////////////
+   // Control path on CS6
+   
+   gpmc_wb gpmc_wb
+     (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
+      .wb_clk(wb_clk), .wb_rst(wb_rst),
+      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),
+      .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
+      .wb_ack_i(wb_ack_i) );
+   
+      assign debug = 0;
+   
+endmodule // gpmc_async
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 31e4fcb69..5fc8134fb 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -21,9 +21,9 @@ module tb_u1e();
    wire [1:0]  EM_NBE;
    
    reg  clk_fpga = 0, rst_fpga = 1;
-   always #15.625 clk_fpga = ~clk_fpga;
+   always #15625 clk_fpga = ~clk_fpga;
 
-   initial #200
+   initial #200000
      @(posedge clk_fpga)
        rst_fpga <= 0;
    
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 7df7b0a48..40950bf82 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -35,22 +35,24 @@ module u1e_core
    wire [35:0] 	 tx_data, rx_data;
    wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy;
    
-   gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
-	      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
-	      .EM_NOE(EM_NOE),
-
-	      .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
-	      
-	      .wb_clk(wb_clk), .wb_rst(wb_rst),
-	      .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
-	      .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
-	      .wb_ack_i(m0_ack),
-
-	      .fifo_clk(wb_clk), .fifo_rst(wb_rst),
-	      .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
-	      .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
-	      
-	      .debug(debug_gpmc));
+   gpmc_async gpmc (.arst(wb_rst),
+		    .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+		    .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
+		    .EM_NOE(EM_NOE),
+		    
+		    .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
+		    .bus_error(), .bus_reset(0),
+		    
+		    .wb_clk(wb_clk), .wb_rst(wb_rst),
+		    .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
+		    .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
+		    .wb_ack_i(m0_ack),
+		    
+		    .fifo_clk(wb_clk), .fifo_rst(wb_rst),
+		    .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
+		    .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
+		    
+		    .debug(debug_gpmc));
 
    fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo
      (.clk(wb_clk), .reset(wb_rst), .clear(0),
-- 
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