From d4649caee02a1c76802dc4f8d7d76bb31b14ce09 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 22:49:02 -0800 Subject: wishbone bridge now with minimal functionality. Need to check timing and handle wait states. --- usrp2/top/u1e/cmdfile | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 usrp2/top/u1e/cmdfile (limited to 'usrp2/top/u1e/cmdfile') diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..5e4db5c65 --- /dev/null +++ b/usrp2/top/u1e/cmdfile @@ -0,0 +1,19 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models + +# Open Cores +-y ../opencores/spi/rtl/verilog ++incdir+../opencores/spi/rtl/verilog +-y ../opencores/i2c/rtl/verilog ++incdir+../opencores/i2c/rtl/verilog + -- cgit v1.2.3 From e56b4767451dcdca41512faba634b812e44d2e1d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 18:03:26 -0800 Subject: Fixed paths to help icarus find opencores and xilinx models. Added Xilinx global set and reset module. --- usrp2/top/u1e/cmdfile | 9 +++++---- usrp2/top/u1e/tb_u1e.v | 2 ++ 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'usrp2/top/u1e/cmdfile') diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile index 5e4db5c65..291c723b8 100644 --- a/usrp2/top/u1e/cmdfile +++ b/usrp2/top/u1e/cmdfile @@ -10,10 +10,11 @@ # Models -y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims # Open Cores --y ../opencores/spi/rtl/verilog -+incdir+../opencores/spi/rtl/verilog --y ../opencores/i2c/rtl/verilog -+incdir+../opencores/i2c/rtl/verilog +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v index 85d2b49f0..319645af6 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/u1e/tb_u1e.v @@ -7,6 +7,8 @@ module tb_u1e(); wire [31:0] debug; wire [1:0] debug_clk; + xlnx_glbl glbl (.GSR(),.GTS()); + initial begin $dumpfile("tb_u1e.lxt"); $dumpvars(0,tb_u1e); -- cgit v1.2.3