From 9f9729993197839d8be950d69eca4456c8e41323 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 28 Jan 2012 12:21:15 -0800 Subject: dsp rework: moved scale and round into ddc chain 16to8 engine now performs only a clip from 16->8 --- usrp2/top/USRP2/u2_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/top/USRP2') diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index f2ca1908b..6c1a418d5 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -441,7 +441,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd8, 16'd3}; //major, minor + localparam compat_num = {16'd9, 16'd0}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), -- cgit v1.2.3