From 2e5effd0b664413c4d3cbbe08d3d841eee051dcc Mon Sep 17 00:00:00 2001 From: Ian Buckley Date: Sat, 31 Jul 2010 00:15:16 -0700 Subject: External FIFO tested in simulation and on USRP2 from decimation 64->8 with current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched. --- usrp2/top/Makefile.common | 1 + 1 file changed, 1 insertion(+) (limited to 'usrp2/top/Makefile.common') diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index d0435fa1e..754471221 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -31,6 +31,7 @@ synth: $(ISE_FILE) $(ISE_HELPER) "Synthesize - XST" bin: $(BIN_FILE) + $(ISE_HELPER) "Generate Programming File" mcs: $(MCS_FILE) -- cgit v1.2.3