From e64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 2 Feb 2012 20:08:47 -0800
Subject: dsp rework: rehash of the custom module stuff and readme

---
 usrp2/top/E1x0/Makefile.E110 | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'usrp2/top/E1x0/Makefile.E110')

diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index 1f95954ae..291ac0a44 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -1,5 +1,5 @@
 #
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
 #
 
 ##################################################
@@ -8,6 +8,10 @@
 TOP_MODULE = u1e
 BUILD_DIR = $(abspath build$(ISE)-E110)
 
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
 ##################################################
 # Include other makefiles
 ##################################################
@@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../gpmc/Makefile.srcs
-include ../../custom/Makefile.srcs
 
 ##################################################
 # Project Properties
@@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
 "Register Balancing" Yes \
 "Use Clock Enable" Auto \
 "Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_MOD_DEFS)"
 
 TRANSLATE_PROPERTIES = \
 "Macro Search Path" "$(shell pwd)/../../coregen/"
-- 
cgit v1.2.3