From 9ecbfeb8ee52b6a59b8757cb259b325cebd05199 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Tue, 17 Jul 2012 12:28:29 -0700
Subject: e100: renamed top level for E100/E110 to E1x0

Some minor tweaks to gpmc_to_fifo + timing
---
 usrp2/top/E1x0/Makefile.E110 | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'usrp2/top/E1x0/Makefile.E110')

diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110
index 8de0714c3..e5be8d2fa 100644
--- a/usrp2/top/E1x0/Makefile.E110
+++ b/usrp2/top/E1x0/Makefile.E110
@@ -5,7 +5,7 @@
 ##################################################
 # Project Setup
 ##################################################
-TOP_MODULE = u1e
+TOP_MODULE = E1x0
 BUILD_DIR = $(abspath build$(ISE)-E110)
 
 # set me in a custom makefile
@@ -49,8 +49,8 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 ##################################################
 TOP_SRCS = \
 ../B100/u1plus_core.v \
-E100.v \
-E100.ucf \
+E1x0.v \
+E1x0.ucf \
 timing.ucf
 
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
-- 
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