From cbea8a3b14412b513b54167b745307a102f2fe68 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 26 Jan 2012 19:00:07 -0800 Subject: dsp rework: u2_core test implementation --- usrp2/top/B100/u1plus_core.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'usrp2/top/B100') diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index c883c5ca8..0a03517b6 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -155,7 +155,7 @@ module u1plus_core wire [35:0] vita_rx_data0; wire vita_rx_src_rdy0, vita_rx_dst_rdy0; - dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 + ddc_chain #(.BASE(SR_RX_DSP0)) ddc_chain0 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), @@ -178,7 +178,7 @@ module u1plus_core wire [35:0] vita_rx_data1; wire vita_rx_src_rdy1, vita_rx_dst_rdy1; - dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + ddc_chain #(.BASE(SR_RX_DSP1)) ddc_chain1 (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_i(adc_i),.adc_ovf_i(0),.adc_q(adc_q),.adc_ovf_q(0), -- cgit v1.2.3