From 42a52c061bdb4873f4672f98e3bcaf17939958a0 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Sat, 24 Mar 2012 21:20:05 -0700
Subject: b100: slave fifo fix for dst/src ready signals

Some of the changes my be overkill,
but the idea is to be more careful about
allowing FIFO IO to occur on transitions.

The cal app was able to complete successfully.
---
 usrp2/top/B100/u1plus_core.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'usrp2/top/B100')

diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index e335fb8bb..26714b669 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -413,7 +413,7 @@ module u1plus_core
    // Readback mux 32 -- Slave #7
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd9, 16'd0}; //major, minor
+   localparam compat_num = {16'd9, 16'd1}; //major, minor
 
    wire [31:0] reg_test32;
 
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