From 8fbedd86500a9d8603ec104369fc3afd833ea2ca Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 9 Dec 2010 18:28:00 -0800 Subject: reimplemented mimo time transfer to handle 64 bits. Still needs to sync on the received side. --- usrp2/timing/time_receiver.v | 96 +++++++++++++++++++++++++++++--------------- 1 file changed, 64 insertions(+), 32 deletions(-) (limited to 'usrp2/timing/time_receiver.v') diff --git a/usrp2/timing/time_receiver.v b/usrp2/timing/time_receiver.v index 8e7d3f1ea..71f0ace90 100644 --- a/usrp2/timing/time_receiver.v +++ b/usrp2/timing/time_receiver.v @@ -1,9 +1,9 @@ module time_receiver (input clk, input rst, - output [31:0] master_time, + output reg [63:0] vita_time, output sync_rcvd, - input exp_pps_in); + input exp_time_in); wire code_err, disp_err, dispout, complete_word; reg disp_reg; @@ -13,7 +13,7 @@ module time_receiver reg [8:0] dataout_reg; always @(posedge clk) - shiftreg <= {exp_pps_in, shiftreg[9:1]}; + shiftreg <= {exp_time_in, shiftreg[9:1]}; localparam COMMA_0 = 10'h283; localparam COMMA_1 = 10'h17c; @@ -55,40 +55,72 @@ module time_receiver localparam STATE_T1 = 2; localparam STATE_T2 = 3; localparam STATE_T3 = 4; + localparam STATE_T4 = 5; + localparam STATE_T5 = 6; + localparam STATE_T6 = 7; + localparam STATE_T7 = 8; + localparam STATE_TAIL = 9; localparam HEAD = 9'h13c; - - reg [7:0] clock_a, clock_b, clock_c; - reg [2:0] state; + localparam TAIL = 9'h1F7; + + reg [3:0] state; always @(posedge clk) if(rst) state <= STATE_IDLE; else if(complete_word) - case(state) - STATE_IDLE : - if(dataout_reg == HEAD) - state <= STATE_T0; - STATE_T0 : - begin - clock_a <= dataout_reg[7:0]; - state <= STATE_T1; - end - STATE_T1 : - begin - clock_b <= dataout_reg[7:0]; - state <= STATE_T2; - end - STATE_T2 : - begin - clock_c <= dataout_reg[7:0]; - state <= STATE_T3; - end - STATE_T3 : - state <= STATE_IDLE; - endcase // case(state) - - assign master_time = {clock_a, clock_b, clock_c, dataout_reg[7:0]}; - assign sync_rcvd = (complete_word & (state == STATE_T3)); - + if(code_err | disp_err) + state <= STATE_IDLE; + else + case(state) + STATE_IDLE : + if(dataout_reg == HEAD) + state <= STATE_T0; + STATE_T0 : + begin + vita_time[63:56] <= dataout_reg[7:0]; + state <= STATE_T1; + end + STATE_T1 : + begin + vita_time[55:48] <= dataout_reg[7:0]; + state <= STATE_T2; + end + STATE_T2 : + begin + vita_time[47:40] <= dataout_reg[7:0]; + state <= STATE_T3; + end + STATE_T3 : + begin + vita_time[39:32] <= dataout_reg[7:0]; + state <= STATE_T4; + end + STATE_T4 : + begin + vita_time[31:24] <= dataout_reg[7:0]; + state <= STATE_T5; + end + STATE_T5 : + begin + vita_time[23:16] <= dataout_reg[7:0]; + state <= STATE_T6; + end + STATE_T6 : + begin + vita_time[15:8] <= dataout_reg[7:0]; + state <= STATE_T7; + end + STATE_T7 : + begin + vita_time[7:0] <= dataout_reg[7:0]; + state <= STATE_TAIL; + end + STATE_TAIL : + state <= STATE_IDLE; + endcase // case(state) + + assign sync_rcvd = (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL)); + endmodule // time_sender -- cgit v1.2.3 From 003df1ee96234f92c17f6c5f19c3c7e0a72490e9 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 10 Dec 2010 00:26:31 -0800 Subject: slave side can now sync --- usrp2/timing/time_64bit.v | 38 +++++++++++++++++++++++++++----------- usrp2/timing/time_receiver.v | 8 ++++++-- 2 files changed, 33 insertions(+), 13 deletions(-) (limited to 'usrp2/timing/time_receiver.v') diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index d3a0e5b2f..a03f437e8 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -15,16 +15,28 @@ module time_64bit localparam PPS_POLSRC = 2; localparam PPS_IMM = 3; localparam TPS = 4; + localparam MIMO_SYNC = 5; reg [31:0] seconds, ticks; wire end_of_second; assign vita_time = {seconds,ticks}; + wire [63:0] vita_time_rcvd; wire [31:0] next_ticks_preset, next_seconds_preset; wire [31:0] ticks_per_sec_reg; wire set_on_pps_trig; reg set_on_next_pps; wire pps_polarity, pps_source, set_imm; + reg [1:0] pps_del; + reg pps_reg_p, pps_reg_n, pps_reg; + wire pps_edge; + + reg [15:0] sync_counter; + wire sync_rcvd; + wire [31:0] mimo_secs, mimo_ticks; + wire mimo_sync_now; + wire mimo_sync; + wire [7:0] sync_delay; setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), @@ -46,10 +58,10 @@ module time_64bit (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(ticks_per_sec_reg),.changed()); - reg [1:0] pps_del; - reg pps_reg_p, pps_reg_n, pps_reg; - wire pps_edge; - + setting_reg #(.my_addr(BASE+MIMO_SYNC), .at_reset(0), .width(9)) sr_mimosync + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({mimo_sync,sync_delay}),.changed()); + always @(posedge clk) pps_reg_p <= pps; always @(negedge clk) pps_reg_n <= pps; always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n; @@ -83,6 +95,11 @@ module time_64bit seconds <= next_seconds_preset; ticks <= next_ticks_preset; end + else if(mimo_sync_now) + begin + seconds <= mimo_secs; + ticks <= mimo_ticks; + end else if(ticks_plus_one == ticks_per_sec_reg) begin seconds <= seconds + 1; @@ -93,11 +110,9 @@ module time_64bit assign pps_int = pps_edge; - localparam SYNC_RATE = 59999; // Send every 600uS - reg [15:0] sync_counter; - wire send_sync = (sync_counter == SYNC_RATE); - wire sync_rcvd; - + // MIMO Connector Time Sync + wire send_sync = (sync_counter == 59999); // X % 10 = 9 + always @(posedge clk) if(rst) sync_counter <= 0; @@ -107,8 +122,6 @@ module time_64bit else sync_counter <= sync_counter + 1; - // must be greater than 1000, 1 less than a multiple of 10; - time_sender time_sender (.clk(clk),.rst(rst), .vita_time(vita_time), @@ -121,5 +134,8 @@ module time_64bit .sync_rcvd(sync_rcvd), .exp_time_in(exp_time_in) ); + assign mimo_secs = vita_time_rcvd[63:32]; + assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay}; + assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC); endmodule // time_64bit diff --git a/usrp2/timing/time_receiver.v b/usrp2/timing/time_receiver.v index 71f0ace90..fd8651d29 100644 --- a/usrp2/timing/time_receiver.v +++ b/usrp2/timing/time_receiver.v @@ -2,7 +2,7 @@ module time_receiver (input clk, input rst, output reg [63:0] vita_time, - output sync_rcvd, + output reg sync_rcvd, input exp_time_in); wire code_err, disp_err, dispout, complete_word; @@ -121,6 +121,10 @@ module time_receiver state <= STATE_IDLE; endcase // case(state) - assign sync_rcvd = (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL)); + always @(posedge clk) + if(rst) + sync_rcvd <= 0; + else + sync_rcvd <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL)); endmodule // time_sender -- cgit v1.2.3