From 8fbedd86500a9d8603ec104369fc3afd833ea2ca Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 9 Dec 2010 18:28:00 -0800 Subject: reimplemented mimo time transfer to handle 64 bits. Still needs to sync on the received side. --- usrp2/timing/time_64bit.v | 42 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) (limited to 'usrp2/timing/time_64bit.v') diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index 51c006962..1889e73da 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -3,12 +3,13 @@ module time_64bit #(parameter TICKS_PER_SEC = 32'd100000000, parameter BASE = 0) - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - input pps, - output [63:0] vita_time, output pps_int - ); - + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input pps, + output [63:0] vita_time, output pps_int, + input exp_time_in, output exp_time_out + ); + localparam NEXT_SECS = 0; localparam NEXT_TICKS = 1; localparam PPS_POLSRC = 2; @@ -91,5 +92,34 @@ module time_64bit ticks <= ticks_plus_one; assign pps_int = pps_edge; + + localparam SYNC_RATE = 59999; // Send every 600uS + reg [15:0] sync_counter; + wire send_sync = (sync_counter == SYNC_RATE); + wire sync_rcvd; + + always @(posedge clk) + if(rst) + sync_counter <= 0; + else + if(send_sync) + sync_counter <= 0; + else + sync_counter <= sync_counter + 1; + + // must be greater than 1000, 1 less than a multiple of 10; + + time_sender time_sender + (.clk(clk),.rst(rst), + .vita_time(vita_time), + .send_sync(send_sync), + .exp_pps_out(exp_pps_out) ); + + time_receiver time_receiver + (.clk(clk),.rst(rst), + .vita_time(vita_time_rcvd), + .sync_rcvd(sync_rcvd), + .exp_pps_in(exp_pps_in) ); + endmodule // time_64bit -- cgit v1.2.3 From 19073f68c864d13c79251e0e9a7ef14acb917a49 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 9 Dec 2010 23:44:53 -0800 Subject: Only do udp now, renamed old ports to exp_time_* --- usrp2/timing/time_64bit.v | 4 +- usrp2/top/u2_rev3/Makefile | 99 ++++++++++++++++++++++++++++++++++++++++++ usrp2/top/u2_rev3/Makefile.udp | 99 ------------------------------------------ 3 files changed, 101 insertions(+), 101 deletions(-) create mode 100644 usrp2/top/u2_rev3/Makefile delete mode 100644 usrp2/top/u2_rev3/Makefile.udp (limited to 'usrp2/timing/time_64bit.v') diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index 1889e73da..d3a0e5b2f 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -113,13 +113,13 @@ module time_64bit (.clk(clk),.rst(rst), .vita_time(vita_time), .send_sync(send_sync), - .exp_pps_out(exp_pps_out) ); + .exp_time_out(exp_time_out) ); time_receiver time_receiver (.clk(clk),.rst(rst), .vita_time(vita_time_rcvd), .sync_rcvd(sync_rcvd), - .exp_pps_in(exp_pps_in) ); + .exp_time_in(exp_time_in) ); endmodule // time_64bit diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile new file mode 100644 index 000000000..05ada2476 --- /dev/null +++ b/usrp2/top/u2_rev3/Makefile @@ -0,0 +1,99 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2_rev3 +BUILD_DIR = $(abspath build) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +PROJECT_PROPERTIES = \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2_core.v \ +u2_rev3.v \ +u2_rev3.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp deleted file mode 100644 index 05ada2476..000000000 --- a/usrp2/top/u2_rev3/Makefile.udp +++ /dev/null @@ -1,99 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# - -################################################## -# Project Setup -################################################## -TOP_MODULE = u2_rev3 -BUILD_DIR = $(abspath build) - -################################################## -# Include other makefiles -################################################## - -include ../Makefile.common -include ../../fifo/Makefile.srcs -include ../../control_lib/Makefile.srcs -include ../../sdr_lib/Makefile.srcs -include ../../serdes/Makefile.srcs -include ../../simple_gemac/Makefile.srcs -include ../../timing/Makefile.srcs -include ../../opencores/Makefile.srcs -include ../../vrt/Makefile.srcs -include ../../udp/Makefile.srcs -include ../../coregen/Makefile.srcs -include ../../extram/Makefile.srcs -include ../../extramfifo/Makefile.srcs - - -################################################## -# Project Properties -################################################## -PROJECT_PROPERTIES = \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -TOP_SRCS = \ -u2_core.v \ -u2_rev3.v \ -u2_rev3.ucf - -SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ -$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ -$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) - -################################################## -# Process Properties -################################################## -SYNTHESIZE_PROPERTIES = \ -"Number of Clock Buffers" 8 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -TRANSLATE_PROPERTIES = \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -MAP_PROPERTIES = \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -PLACE_ROUTE_PROPERTIES = \ -"Place & Route Effort Level (Overall)" High - -STATIC_TIMING_PROPERTIES = \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -GEN_PROG_FILE_PROPERTIES = \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -SIM_MODEL_PROPERTIES = "" -- cgit v1.2.3 From 003df1ee96234f92c17f6c5f19c3c7e0a72490e9 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 10 Dec 2010 00:26:31 -0800 Subject: slave side can now sync --- usrp2/timing/time_64bit.v | 38 +++++++++++++++++++++++++++----------- usrp2/timing/time_receiver.v | 8 ++++++-- 2 files changed, 33 insertions(+), 13 deletions(-) (limited to 'usrp2/timing/time_64bit.v') diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index d3a0e5b2f..a03f437e8 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -15,16 +15,28 @@ module time_64bit localparam PPS_POLSRC = 2; localparam PPS_IMM = 3; localparam TPS = 4; + localparam MIMO_SYNC = 5; reg [31:0] seconds, ticks; wire end_of_second; assign vita_time = {seconds,ticks}; + wire [63:0] vita_time_rcvd; wire [31:0] next_ticks_preset, next_seconds_preset; wire [31:0] ticks_per_sec_reg; wire set_on_pps_trig; reg set_on_next_pps; wire pps_polarity, pps_source, set_imm; + reg [1:0] pps_del; + reg pps_reg_p, pps_reg_n, pps_reg; + wire pps_edge; + + reg [15:0] sync_counter; + wire sync_rcvd; + wire [31:0] mimo_secs, mimo_ticks; + wire mimo_sync_now; + wire mimo_sync; + wire [7:0] sync_delay; setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), @@ -46,10 +58,10 @@ module time_64bit (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(ticks_per_sec_reg),.changed()); - reg [1:0] pps_del; - reg pps_reg_p, pps_reg_n, pps_reg; - wire pps_edge; - + setting_reg #(.my_addr(BASE+MIMO_SYNC), .at_reset(0), .width(9)) sr_mimosync + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({mimo_sync,sync_delay}),.changed()); + always @(posedge clk) pps_reg_p <= pps; always @(negedge clk) pps_reg_n <= pps; always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n; @@ -83,6 +95,11 @@ module time_64bit seconds <= next_seconds_preset; ticks <= next_ticks_preset; end + else if(mimo_sync_now) + begin + seconds <= mimo_secs; + ticks <= mimo_ticks; + end else if(ticks_plus_one == ticks_per_sec_reg) begin seconds <= seconds + 1; @@ -93,11 +110,9 @@ module time_64bit assign pps_int = pps_edge; - localparam SYNC_RATE = 59999; // Send every 600uS - reg [15:0] sync_counter; - wire send_sync = (sync_counter == SYNC_RATE); - wire sync_rcvd; - + // MIMO Connector Time Sync + wire send_sync = (sync_counter == 59999); // X % 10 = 9 + always @(posedge clk) if(rst) sync_counter <= 0; @@ -107,8 +122,6 @@ module time_64bit else sync_counter <= sync_counter + 1; - // must be greater than 1000, 1 less than a multiple of 10; - time_sender time_sender (.clk(clk),.rst(rst), .vita_time(vita_time), @@ -121,5 +134,8 @@ module time_64bit .sync_rcvd(sync_rcvd), .exp_time_in(exp_time_in) ); + assign mimo_secs = vita_time_rcvd[63:32]; + assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay}; + assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC); endmodule // time_64bit diff --git a/usrp2/timing/time_receiver.v b/usrp2/timing/time_receiver.v index 71f0ace90..fd8651d29 100644 --- a/usrp2/timing/time_receiver.v +++ b/usrp2/timing/time_receiver.v @@ -2,7 +2,7 @@ module time_receiver (input clk, input rst, output reg [63:0] vita_time, - output sync_rcvd, + output reg sync_rcvd, input exp_time_in); wire code_err, disp_err, dispout, complete_word; @@ -121,6 +121,10 @@ module time_receiver state <= STATE_IDLE; endcase // case(state) - assign sync_rcvd = (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL)); + always @(posedge clk) + if(rst) + sync_rcvd <= 0; + else + sync_rcvd <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL)); endmodule // time_sender -- cgit v1.2.3 From c97440838aa740fc335c59914f6dfd6f492b69f8 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 10 Dec 2010 10:49:59 -0800 Subject: time sync on usrp2 as well, added debug pins to time sync. --- usrp2/timing/time_64bit.v | 6 +++++- usrp2/top/u2_rev3/u2_core.v | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'usrp2/timing/time_64bit.v') diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index a03f437e8..33eb2b25a 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -7,7 +7,8 @@ module time_64bit input set_stb, input [7:0] set_addr, input [31:0] set_data, input pps, output [63:0] vita_time, output pps_int, - input exp_time_in, output exp_time_out + input exp_time_in, output exp_time_out, + output [31:0] debug ); localparam NEXT_SECS = 0; @@ -137,5 +138,8 @@ module time_64bit assign mimo_secs = vita_time_rcvd[63:32]; assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay}; assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC); + + assign debug = { { 24'b0} , + { 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} }; endmodule // time_64bit diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index c2d473650..30b47b818 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -720,9 +720,13 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // VITA Timing + wire [31:0] debug_sync; + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), + .debug(debug_sync)); // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins -- cgit v1.2.3