From f2ea250dc491c284bbfa895c79a44e5f4f34c484 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 12 May 2011 23:43:19 -0700
Subject: dsp: reorganized scaling and rounding, removed multipliers (will put
back in a different location)
---
usrp2/sdr_lib/dsp_core_rx.v | 56 ++++++++++++++++++++----------------------
usrp2/sdr_lib/dsp_core_rx_tb.v | 4 +--
usrp2/sdr_lib/hb_dec.v | 35 +++++++++++++-------------
3 files changed, 46 insertions(+), 49 deletions(-)
(limited to 'usrp2/sdr_lib')
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index ca1e0d5b4..19215c777 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -39,8 +39,7 @@ module dsp_core_rx
wire [23:0] i_cic, q_cic;
wire [17:0] i_cic_scaled, q_cic_scaled;
wire [17:0] i_hb1, q_hb1;
- wire [17:0] i_hb2, q_hb2;
- wire [15:0] i_out, q_out;
+ wire [15:0] i_hb2, q_hb2;
wire strobe_cic, strobe_hb1, strobe_hb2;
wire enable_hb1, enable_hb2;
@@ -86,27 +85,9 @@ module dsp_core_rx
else
phase <= phase + phase_inc;
- MULT18X18S mult_i
- (.P(prod_i), // 36-bit multiplier output
- .A(adc_i_mux), // 18-bit multiplier input
- .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input
- .C(clk), // Clock input
- .CE(1), // Clock enable input
- .R(rst) // Synchronous reset input
- );
-
- MULT18X18S mult_q
- (.P(prod_q), // 36-bit multiplier output
- .A(adc_q_mux), // 18-bit multiplier input
- .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input
- .C(clk), // Clock input
- .CE(1), // Clock enable input
- .R(rst) // Synchronous reset input
- );
-
cordic_z24 #(.bitwidth(24))
cordic(.clock(clk), .reset(rst), .enable(run),
- .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]),
+ .xi({adc_i_mux,6'd0}),. yi({adc_q_mux,6'd0}), .zi(phase[31:8]),
.xo(i_cordic),.yo(q_cordic),.zo() );
cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
@@ -138,21 +119,38 @@ module dsp_core_rx
.stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1));
wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
- hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i
+ hb_dec #(.IWIDTH(18), .OWIDTH(16), .CWIDTH(18), .ACCWIDTH(24)) hb_i
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
.stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
- hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q
+ hb_dec #(.IWIDTH(18), .OWIDTH(16), .CWIDTH(18), .ACCWIDTH(24)) hb_q
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
.stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
- round_sd #(.WIDTH_IN(18),.WIDTH_OUT(16)) round_iout
- (.clk(clk), .reset(rst), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
-
- round_sd #(.WIDTH_IN(18),.WIDTH_OUT(16)) round_qout
- (.clk(clk), .reset(rst), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
+ assign sample = {i_hb2,q_hb2};
+ assign strobe = strobe_hb2;
- assign sample = {i_out,q_out};
assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
endmodule // dsp_core_rx
+
+/*
+ MULT18X18S mult_i
+ (.P(prod_i), // 36-bit multiplier output
+ .A(adc_i_mux), // 18-bit multiplier input
+ .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input
+ .C(clk), // Clock input
+ .CE(1), // Clock enable input
+ .R(rst) // Synchronous reset input
+ );
+
+ MULT18X18S mult_q
+ (.P(prod_q), // 36-bit multiplier output
+ .A(adc_q_mux), // 18-bit multiplier input
+ .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input
+ .C(clk), // Clock input
+ .CE(1), // Clock enable input
+ .R(rst) // Synchronous reset input
+ );
+
+*/
diff --git a/usrp2/sdr_lib/dsp_core_rx_tb.v b/usrp2/sdr_lib/dsp_core_rx_tb.v
index 991b3a850..c8fb33982 100644
--- a/usrp2/sdr_lib/dsp_core_rx_tb.v
+++ b/usrp2/sdr_lib/dsp_core_rx_tb.v
@@ -46,11 +46,11 @@ module dsp_core_rx_tb();
@(negedge rst);
@(posedge clk);
set_addr <= 1;
- set_data <= {16'd1024,16'd1024};
+ set_data <= {16'd64,16'd64};
set_stb <= 1;
@(posedge clk);
set_addr <= 2;
- set_data <= 8;
+ set_data <= {16'd0,8'd3,8'd8};
set_stb <= 1;
@(posedge clk);
set_stb <= 0;
diff --git a/usrp2/sdr_lib/hb_dec.v b/usrp2/sdr_lib/hb_dec.v
index 9747f0adb..59c66ea28 100644
--- a/usrp2/sdr_lib/hb_dec.v
+++ b/usrp2/sdr_lib/hb_dec.v
@@ -30,8 +30,8 @@ module hb_dec
input [8:0] cpi, // Clocks per input -- equal to the decimation ratio ahead of this block
input stb_in,
input [IWIDTH-1:0] data_in,
- output reg stb_out,
- output reg [OWIDTH-1:0] data_out);
+ output stb_out,
+ output [OWIDTH-1:0] data_out);
// Control
reg [3:0] addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d;
@@ -167,22 +167,21 @@ module hb_dec
add2_reg /* add2_and_round_reg */ #(.WIDTH(ACCWIDTH+1))
final_adder (.clk(clk), .in1({acc_out,1'b0}), .in2({data_even_signext,1'b0}), .sum(final_sum_unrounded));
- round_reg #(.bits_in(ACCWIDTH-4),.bits_out(OWIDTH))
- final_round (.clk(clk),.in(final_sum_unrounded[ACCWIDTH-5:0]),.out(final_sum));
+ wire [OWIDTH-1:0] bypass_data;
+ wire stb_final, stb_bypass;
+
+ round_sd #(.WIDTH_IN(ACCWIDTH-4),.WIDTH_OUT(OWIDTH))
+ final_round (.clk(clk),.reset(rst),
+ .in(final_sum_unrounded[ACCWIDTH-5:0]),.strobe_in(stb_out_pre[9]),
+ .out(final_sum), .strobe_out(stb_final));
- // Output
- always @(posedge clk)
- if(bypass)
- data_out <= data_in;
- else if(stb_out_pre[9])
- data_out <= final_sum;
+ round_sd #(.WIDTH_IN(IWIDTH),.WIDTH_OUT(OWIDTH))
+ bypass_round (.clk(clk),.reset(rst),
+ .in(data_in),.strobe_in(stb_in),
+ .out(bypass_data), .strobe_out(stb_bypass));
- always @(posedge clk)
- if(rst)
- stb_out <= 0;
- else if(bypass)
- stb_out <= stb_in;
- else
- stb_out <= stb_out_pre[9];
-
+ // Output
+ assign stb_out = bypass ? stb_bypass : stb_final;
+ assign data_out = bypass ? bypass_data : final_sum;
+
endmodule // hb_dec
--
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