From ce43cdfc6782b9f24781170f8f78a96e93bb2365 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Sun, 5 Dec 2010 20:33:05 -0800
Subject: redone DC offset with sigma-delta quantization

---
 usrp2/sdr_lib/add2_and_clip.v     | 12 +++++++++
 usrp2/sdr_lib/add2_and_clip_reg.v | 20 +++++++++++++++
 usrp2/sdr_lib/round.v             |  4 ++-
 usrp2/sdr_lib/rx_dcoffset.v       | 51 ++++++++++++++++++++++-----------------
 usrp2/sdr_lib/rx_dcoffset_tb.v    | 20 ++++++++++++---
 5 files changed, 80 insertions(+), 27 deletions(-)
 create mode 100644 usrp2/sdr_lib/add2_and_clip.v
 create mode 100644 usrp2/sdr_lib/add2_and_clip_reg.v

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/add2_and_clip.v b/usrp2/sdr_lib/add2_and_clip.v
new file mode 100644
index 000000000..663f5d004
--- /dev/null
+++ b/usrp2/sdr_lib/add2_and_clip.v
@@ -0,0 +1,12 @@
+
+module add2_and_clip
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip
+     (.in(sum_int),.out(sum));
+   
+endmodule // add2_and_clip
diff --git a/usrp2/sdr_lib/add2_and_clip_reg.v b/usrp2/sdr_lib/add2_and_clip_reg.v
new file mode 100644
index 000000000..7070f1cea
--- /dev/null
+++ b/usrp2/sdr_lib/add2_and_clip_reg.v
@@ -0,0 +1,20 @@
+
+module add2_and_clip_reg
+  #(parameter WIDTH=16)
+    (input clk,
+     input rst,
+     input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output reg [WIDTH-1:0] sum);
+
+   wire [WIDTH-1:0] sum_int;
+   
+   add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int));
+
+   always @(posedge clk)
+     if(rst)
+       sum <= 0;
+     else
+       sum <= sum_int;
+   
+endmodule // add2_and_clip_reg
diff --git a/usrp2/sdr_lib/round.v b/usrp2/sdr_lib/round.v
index c4f9ec9cd..7a137d702 100644
--- a/usrp2/sdr_lib/round.v
+++ b/usrp2/sdr_lib/round.v
@@ -26,8 +26,10 @@ module round
   #(parameter bits_in=0,
     parameter bits_out=0)
     (input [bits_in-1:0] in,
-     output [bits_out-1:0] out);
+     output [bits_out-1:0] out,
+     output [bits_in-bits_out:0] err);
 
    assign out = in[bits_in-1:bits_in-bits_out] + (in[bits_in-1] & |in[bits_in-bits_out-1:0]);
+   assign err = in - {out,{(bits_in-bits_out){1'b0}}};
    
 endmodule // round
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 64ff4110d..35dfb07ae 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -18,43 +18,50 @@
 
 
 module rx_dcoffset 
-  #(parameter WIDTH=14,
-    parameter ADDR=8'd0)
-    (input clk, input rst, 
-     input set_stb, input [7:0] set_addr, input [31:0] set_data,
-     input signed [WIDTH-1:0] adc_in, output signed [WIDTH-1:0] adc_out);
-
-   // Because of some extra delays to make timing easier, the transfer function is:
-   //     (z-1)/(z^2-z-alpha)  where alpha is 1/2^n
+  #(parameter WIDTH=16,
+    parameter ADDR=8'd0,
+    parameter alpha_shift=16)
+   (input clk, input rst, 
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [WIDTH-1:0] in, output [WIDTH-1:0] out);
    
-   wire 	       set_now = set_stb & (ADDR == set_addr);
+   wire 	      set_now = set_stb & (ADDR == set_addr);
    
-   reg 		       fixed;  // uses fixed offset
-   wire 	       signed [WIDTH-1:0] fixed_dco;
-   reg 		       signed [31:0] integrator;
+   reg 		      fixed;  // uses fixed offset
+   wire [WIDTH-1:0]   fixed_dco;
 
+   localparam int_width = WIDTH + alpha_shift;
+   reg [int_width-1:0] integrator;
+   
    always @(posedge clk)
      if(rst)
        begin
 	  fixed <= 0;
-	  integrator <= 32'd0;
+	  integrator <= {int_width{1'b0}};
        end
      else if(set_now)
        begin
-	  integrator <= {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}};
+	  //integrator <= {set_data[30:0],{(31-int_width){1'b0}}};
 	  fixed <= set_data[31];
        end
      else if(~fixed)
-       integrator <= integrator + adc_out;
-   
-   wire [WIDTH:0] scaled_integrator;
+       integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
+
+   wire [WIDTH-1:0] quantized;
+   wire [int_width-WIDTH:0] q_err;
+   wire [int_width-1:0]     q_err_ext;
+   wire [int_width-1:0]     q_loop;
+
+   round #(.bits_in(int_width), .bits_out(WIDTH)) quantizer
+     (.in(q_loop), .out(quantized), .err(q_err));
    
-   round #(.bits_in(33),.bits_out(15)) round (.in({integrator[31],integrator}),.out(scaled_integrator));
+   sign_extend #(.bits_in(int_width-WIDTH+1),.bits_out(int_width)) sign_extend
+     (.in(q_err), .out(q_err_ext));
    
-   wire [WIDTH:0]      adc_out_int = {adc_in[WIDTH-1],adc_in} - scaled_integrator;
-
-   clip_reg #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip_adc
-     (.clk(clk),.in(adc_out_int),.out(adc_out));
+   add2_and_clip_reg #(.WIDTH(int_width)) sd_fixed
+     (.clk(clk), .rst(rst), .in1(integrator), .in2(q_err_ext), .sum(q_loop));
    
+   add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
+     (.clk(clk), .in1(in), .in2(-quantized), .sum(out));
 
 endmodule // rx_dcoffset
diff --git a/usrp2/sdr_lib/rx_dcoffset_tb.v b/usrp2/sdr_lib/rx_dcoffset_tb.v
index b0dd8cb05..b4fb66ad7 100644
--- a/usrp2/sdr_lib/rx_dcoffset_tb.v
+++ b/usrp2/sdr_lib/rx_dcoffset_tb.v
@@ -29,14 +29,26 @@ module rx_dcoffset_tb();
    initial $dumpfile("rx_dcoffset_tb.vcd");
    initial $dumpvars(0,rx_dcoffset_tb);
 
-   reg [13:0] adc_in = 7;
+   reg [13:0] adc_in;
    wire [13:0] adc_out;
 
    always @(posedge clk)
-     $display("%d\t%d",adc_in,adc_out);
+     begin
+	if(adc_in[13])
+	  $write("-%d,",-adc_in);
+	else
+	  $write("%d,",adc_in);
+	if(adc_out[13])
+	  $write("-%d\n",-adc_out);
+	else
+	  $write("%d\n",adc_out);
+     end	
    
-   rx_dcoffset #(.WIDTH(14),.ADDR(0))
+   rx_dcoffset #(.WIDTH(14),.ADDR(0), .alpha_shift(8))
      rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0),
-		 .adc_in(adc_in),.adc_out(adc_out));
+		 .in(adc_in),.out(adc_out));
+
+   always @(posedge clk)
+     adc_in <= (($random % 473) + 23)/4;
    
 endmodule // longfifo_tb
-- 
cgit v1.2.3


From f8a04a4879260b2692b823a067a63c3ca5e35731 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 7 Mar 2011 23:09:06 -0800
Subject: u2/u2p:  pull IQ balance and dcoffset out of dsp_core, put in
 frontend module

---
 usrp2/sdr_lib/dsp_core_rx.v | 43 ++------------------------
 usrp2/sdr_lib/rx_dcoffset.v |  2 +-
 usrp2/sdr_lib/rx_frontend.v | 75 +++++++++++++++++++++++++++++++++++++++++++++
 usrp2/top/USRP2/u2_core.v   | 15 +++++++--
 4 files changed, 91 insertions(+), 44 deletions(-)
 create mode 100644 usrp2/sdr_lib/rx_frontend.v

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 0e69e53f7..9aee52131 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -21,8 +21,8 @@ module dsp_core_rx
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
-   input [13:0] adc_a, input adc_ovf_a,
-   input [13:0] adc_b, input adc_ovf_b,
+   input [17:0] adc_i, input adc_ovf_a,
+   input [17:0] adc_q, input adc_ovf_b,
    
    output [31:0] sample,
    input run,
@@ -60,40 +60,6 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
 
-   rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a
-     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .adc_in(adc_a),.adc_out(adc_a_ofs));
-   
-   rx_dcoffset #(.WIDTH(14),.ADDR(BASE+4)) rx_dcoffset_b
-     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .adc_in(adc_b),.adc_out(adc_b_ofs));
-
-   wire [7:0]  muxctrl;
-   setting_reg #(.my_addr(BASE+5), .width(8)) sr_8
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(muxctrl),.changed());
-
-   wire [1:0] gpio_ena;
-   setting_reg #(.my_addr(BASE+6), .width(2)) sr_9
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(gpio_ena),.changed());
-
-   always @(posedge clk)
-     case(muxctrl[3:0])		// The I mapping
-       0: adc_i <= adc_a_ofs;
-       1: adc_i <= adc_b_ofs;
-       2: adc_i <= 0;
-       default: adc_i <= 0;
-     endcase // case (muxctrl[3:0])
-   
-   always @(posedge clk)
-     case(muxctrl[7:4])		// The Q mapping
-       0: adc_q <= adc_a_ofs;
-       1: adc_q <= adc_b_ofs;
-       2: adc_q <= 0;
-       default: adc_q <= 0;
-     endcase // case (muxctrl[7:4])
-          
    always @(posedge clk)
      if(rst)
        phase <= 0;
@@ -119,7 +85,6 @@ module dsp_core_rx
       .CE(1),  // Clock enable input
       .R(rst)     // Synchronous reset input
       ); 
-
    
    cordic_z24 #(.bitwidth(24))
      cordic(.clock(clk), .reset(rst), .enable(run),
@@ -164,10 +129,6 @@ module dsp_core_rx
    round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out));
    round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out));
 
-   reg [31:0] sample_reg;
-   always @(posedge clk)
-     sample_reg <= {i_out,q_out};
-   
    assign      sample = sample_reg;
    assign      strobe = strobe_hb2;
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 35dfb07ae..52f8cd5be 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -62,6 +62,6 @@ module rx_dcoffset
      (.clk(clk), .rst(rst), .in1(integrator), .in2(q_err_ext), .sum(q_loop));
    
    add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
-     (.clk(clk), .in1(in), .in2(-quantized), .sum(out));
+     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .sum(out));
 
 endmodule // rx_dcoffset
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
new file mode 100644
index 000000000..f5271a207
--- /dev/null
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -0,0 +1,75 @@
+
+module rx_frontend
+  #(parameter BASE = 0)
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [15:0] adc_a, input adc_ovf_a,
+    input [15:0] adc_b, input adc_ovf_b,
+
+    output [17:0] i_out, output [17:0] q_out,
+    input run,
+    output [31:0] debug
+    );
+   
+   reg [15:0] 	  adc_i, adc_q;
+   wire [17:0] 	  adc_i_ofs, adc_q_ofs;
+   wire [35:0] 	  corr_i, corr_q;
+   wire [17:0] 	  scale_i, scale_q;
+   wire [7:0] 	  muxctrl;
+   wire [23:0] 	  i_final, q_final;
+   
+   setting_reg #(.my_addr(BASE), .width(8)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(muxctrl),.changed());
+
+   always @(posedge clk)
+     case(muxctrl[3:0])		// The I mapping
+       0: adc_i <= adc_a;
+       1: adc_i <= adc_b;
+       2: adc_i <= 0;
+       default: adc_i <= 0;
+     endcase // case (muxctrl[3:0])
+   
+   always @(posedge clk)
+     case(muxctrl[7:4])		// The Q mapping
+       0: adc_q <= adc_a;
+       1: adc_q <= adc_b;
+       2: adc_q <= 0;
+       default: adc_q <= 0;
+     endcase // case (muxctrl[7:4])
+   
+   setting_reg #(.my_addr(BASE+1),.width(18)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(scale_i),.changed());
+   
+   setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(scale_q),.changed());
+   
+   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .in({adc_i,2'b00}),.out(adc_i_ofs));
+   
+   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .in({adc_q,2'b00}),.out(adc_q_ofs));
+   
+   MULT18X18S mult_i
+     (.P(corr_q), .A(adc_i_ofs), .B(scale_i), .C(clk), .CE(1), .R(rst) );
+   
+   MULT18X18S mult_q
+     (.P(corr_i), .A(adc_i_ofs), .B(scale_q), .C(clk), .CE(1), .R(rst) ); 
+
+   add2_and_clip_reg #(.WIDTH(24)) add_clip_i
+     (.clk(clk), .rst(rst), 
+      .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final));
+   
+   add2_and_clip_reg #(.WIDTH(24)) add_clip_q
+     (.clk(clk), .rst(rst), 
+      .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final));
+
+   assign i_out = i_final[23:6];
+   assign q_out = q_final[23:6];
+   
+endmodule // rx_frontend
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index ca9762ac5..691b60c1c 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -582,6 +582,17 @@ module u2_core
 
    assign sd_dat_i[31:8] = 0;
 
+   // /////////////////////////////////////////////////////////////////////////
+   // ADC Frontend
+   wire [17:0] 	 adc_i, adc_q;
+   
+   rx_frontend #(.BASE()) rx_frontend
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a),
+      .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b),
+      .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug());
+   
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 0
    wire [31:0] 	 sample_rx0;
@@ -593,7 +604,7 @@ module u2_core
    dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b),
       .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
       .debug() );
 
@@ -621,7 +632,7 @@ module u2_core
    dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b),
       .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
       .debug() );
 
-- 
cgit v1.2.3


From 883d5af46bf756908a2fe45dea8a7d3673f7cb0a Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 11 Mar 2011 10:31:55 -0800
Subject: unused nets

---
 usrp2/sdr_lib/dsp_core_rx.v | 1 -
 1 file changed, 1 deletion(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 9aee52131..36d56174e 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -31,7 +31,6 @@ module dsp_core_rx
    );
 
    wire [15:0] scale_i, scale_q;
-   wire [13:0] adc_a_ofs, adc_b_ofs;
    reg [13:0] adc_i, adc_q;
    wire [31:0] phase_inc;
    reg [31:0]  phase;
-- 
cgit v1.2.3


From 2bad9b4d2711ad3aeef2e3b35153b2463874940e Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 11 Mar 2011 13:43:51 -0800
Subject: u2/u2p: misc connection and compilation fixes

---
 usrp2/sdr_lib/Makefile.srcs |  1 +
 usrp2/sdr_lib/dsp_core_rx.v | 21 +++++++++++----------
 usrp2/sdr_lib/rx_frontend.v | 16 ++++++++--------
 usrp2/top/USRP2/u2_core.v   |  4 ++--
 4 files changed, 22 insertions(+), 20 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/Makefile.srcs b/usrp2/sdr_lib/Makefile.srcs
index 90eede20f..4a85726a9 100644
--- a/usrp2/sdr_lib/Makefile.srcs
+++ b/usrp2/sdr_lib/Makefile.srcs
@@ -30,6 +30,7 @@ round.v \
 round_reg.v \
 rx_control.v \
 rx_dcoffset.v \
+rx_frontend.v \
 sign_extend.v \
 small_hb_dec.v \
 small_hb_int.v \
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 36d56174e..ae6cdbdf3 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -21,8 +21,8 @@ module dsp_core_rx
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
-   input [17:0] adc_i, input adc_ovf_a,
-   input [17:0] adc_q, input adc_ovf_b,
+   input [17:0] adc_i, input adc_ovf_i,
+   input [17:0] adc_q, input adc_ovf_q,
    
    output [31:0] sample,
    input run,
@@ -31,7 +31,6 @@ module dsp_core_rx
    );
 
    wire [15:0] scale_i, scale_q;
-   reg [13:0] adc_i, adc_q;
    wire [31:0] phase_inc;
    reg [31:0]  phase;
 
@@ -69,7 +68,7 @@ module dsp_core_rx
 
    MULT18X18S mult_i
      (.P(prod_i),    // 36-bit multiplier output
-      .A({{4{adc_i[13]}},adc_i} ),    // 18-bit multiplier input
+      .A(adc_i),    // 18-bit multiplier input
       .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input
@@ -78,7 +77,7 @@ module dsp_core_rx
 
    MULT18X18S mult_q
      (.P(prod_q),    // 36-bit multiplier output
-      .A({{4{adc_q[13]}},adc_q} ),    // 18-bit multiplier input
+      .A(adc_q),    // 18-bit multiplier input
       .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input
@@ -125,11 +124,13 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
-   round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out));
-   round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out));
-
-   assign      sample = sample_reg;
-   assign      strobe = strobe_hb2;
+   round_reg #(.bits_in(18),.bits_out(16)) round_iout (.clk(clk),.in(i_hb2),.out(i_out));
+   round_reg #(.bits_in(18),.bits_out(16)) round_qout (.clk(clk),.in(q_hb2),.out(q_out));
+   reg 	       strobe_out;
+   always @(posedge clk) strobe_out <= strobe_hb2;
+   
+   assign      sample = {i_hb2,q_hb2};
+   assign      strobe = strobe_out;
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
    
 endmodule // dsp_core_rx
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index f5271a207..3b05a4a08 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -15,7 +15,7 @@ module rx_frontend
    reg [15:0] 	  adc_i, adc_q;
    wire [17:0] 	  adc_i_ofs, adc_q_ofs;
    wire [35:0] 	  corr_i, corr_q;
-   wire [17:0] 	  scale_i, scale_q;
+   wire [17:0] 	  mag_corr,phase_corr;
    wire [7:0] 	  muxctrl;
    wire [23:0] 	  i_final, q_final;
    
@@ -41,11 +41,11 @@ module rx_frontend
    
    setting_reg #(.my_addr(BASE+1),.width(18)) sr_1
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(scale_i),.changed());
+      .in(set_data),.out(mag_corr),.changed());
    
    setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(scale_q),.changed());
+      .in(set_data),.out(phase_corr),.changed());
    
    rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i
      (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -55,12 +55,12 @@ module rx_frontend
      (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .in({adc_q,2'b00}),.out(adc_q_ofs));
    
-   MULT18X18S mult_i
-     (.P(corr_q), .A(adc_i_ofs), .B(scale_i), .C(clk), .CE(1), .R(rst) );
-   
-   MULT18X18S mult_q
-     (.P(corr_i), .A(adc_i_ofs), .B(scale_q), .C(clk), .CE(1), .R(rst) ); 
+   MULT18X18S mult_mag_corr
+     (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); 
 
+   MULT18X18S mult_phase_corr
+     (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
+   
    add2_and_clip_reg #(.WIDTH(24)) add_clip_i
      (.clk(clk), .rst(rst), 
       .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final));
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 691b60c1c..151ac27ae 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -604,7 +604,7 @@ module u2_core
    dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-      .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b),
+      .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),
       .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
       .debug() );
 
@@ -632,7 +632,7 @@ module u2_core
    dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-      .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b),
+      .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),
       .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
       .debug() );
 
-- 
cgit v1.2.3


From 47967a432248cacf6b17add35263308ecc0526f4 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 4 Apr 2011 08:16:33 -0700
Subject: dsp: pass the error through in the rounding function

---
 usrp2/sdr_lib/round_reg.v | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/round_reg.v b/usrp2/sdr_lib/round_reg.v
index aa0972dab..6f2e974d7 100644
--- a/usrp2/sdr_lib/round_reg.v
+++ b/usrp2/sdr_lib/round_reg.v
@@ -27,13 +27,18 @@ module round_reg
     parameter bits_out=0)
     (input clk,
      input [bits_in-1:0] in,
-     output reg [bits_out-1:0] out);
+     output reg [bits_out-1:0] out,
+     output reg [bits_in-bits_out:0] err);
 
    wire [bits_out-1:0] temp;
-
-   round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp));
+   wire [bits_in-bits_out:0] err_temp;
+   
+   round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp), .err(err_temp));
    
    always @(posedge clk)
      out <= temp;
+
+   always @(posedge clk)
+     err <= err_temp;
    
-endmodule // round
+endmodule // round_reg
-- 
cgit v1.2.3


From b97319808eb9108d7f1ac63b085b4557ce6b5acb Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 4 Apr 2011 09:07:06 -0700
Subject: dsp: first cut at sigma-delta rounding

---
 usrp2/sdr_lib/round_sd.v    | 43 +++++++++++++++++++++++++++++++++++++++
 usrp2/sdr_lib/round_sd_tb.v | 49 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 92 insertions(+)
 create mode 100644 usrp2/sdr_lib/round_sd.v
 create mode 100644 usrp2/sdr_lib/round_sd_tb.v

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/round_sd.v b/usrp2/sdr_lib/round_sd.v
new file mode 100644
index 000000000..9c2a69615
--- /dev/null
+++ b/usrp2/sdr_lib/round_sd.v
@@ -0,0 +1,43 @@
+
+
+module round_sd
+  #(parameter WIDTH_IN=18,
+    parameter WIDTH_OUT=16)
+   (input clk, input reset,
+    input [WIDTH_IN-1:0] in, output [WIDTH_OUT-1:0] out);
+
+   localparam SUM_WIDTH = WIDTH_IN+1;
+   localparam ERR_WIDTH = SUM_WIDTH - (WIDTH_OUT + 1) + 1;
+   localparam ACC_WIDTH = ERR_WIDTH + 1;
+   
+   reg [ACC_WIDTH-1:0] 	 acc;
+   wire [SUM_WIDTH-1:0] acc_ext, in_ext;
+
+   sign_extend #(.bits_in(WIDTH_IN),.bits_out(SUM_WIDTH)) ext_in (.in(in), .out(in_ext));
+   sign_extend #(.bits_in(ACC_WIDTH),.bits_out(SUM_WIDTH)) ext_acc (.in(acc), .out(acc_ext));
+   
+   wire [SUM_WIDTH-1:0] sum = in_ext + acc_ext;
+   wire [WIDTH_OUT:0] 	sum_round;
+   wire [ERR_WIDTH-1:0] err;
+   wire [ACC_WIDTH-1:0] err_ext;
+   
+   //round_reg #(.bits_in(SUM_WIDTH),.bits_out(WIDTH_OUT+1))  round_sum (.clk(clk), .in(sum), .out(sum_round));
+   round #(.bits_in(SUM_WIDTH),.bits_out(WIDTH_OUT+1))  round_sum ( .in(sum), .out(sum_round));
+
+   reg [WIDTH_IN-1:0] 	in_del;
+   always @(posedge clk)
+     in_del <= in;
+   
+   assign err = in_del - {sum_round,{SUM_WIDTH-WIDTH_OUT-1{1'b0}}};
+   
+   clip #(.bits_in(WIDTH_OUT+1),.bits_out(WIDTH_OUT)) clip (.in(sum_round), .out(out));
+
+   sign_extend #(.bits_in(ERR_WIDTH),.bits_out(ACC_WIDTH)) ext_err (.in(err), .out(err_ext));
+   
+   always @(posedge clk)
+     if(reset)
+       acc <= 0;
+     else
+       acc <= acc + err_ext;
+   
+endmodule // rx_dcoffset
diff --git a/usrp2/sdr_lib/round_sd_tb.v b/usrp2/sdr_lib/round_sd_tb.v
new file mode 100644
index 000000000..df9f58421
--- /dev/null
+++ b/usrp2/sdr_lib/round_sd_tb.v
@@ -0,0 +1,49 @@
+
+module round_sd_tb();
+   
+   reg clk, rst;
+
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #5 clk = ~clk;
+   
+   initial $dumpfile("round_sd_tb.vcd");
+   initial $dumpvars(0,round_sd_tb);
+
+   localparam WIDTH_IN = 14;
+   localparam WIDTH_OUT = 10;
+   
+   reg [WIDTH_IN-1:0] adc_in, adc_in_del;
+   wire [WIDTH_OUT-1:0] adc_out;
+
+   integer 		factor = 1<<(WIDTH_IN-WIDTH_OUT);
+   
+   always @(posedge clk)
+     if(~rst)
+	begin  
+	   if(adc_in_del[WIDTH_IN-1])
+	     $write("-%d\t",-adc_in_del);
+	   else
+	     $write("%d\t",adc_in_del);
+	   if(adc_out[WIDTH_OUT-1])
+	     $write("-%d\t",-adc_out);
+	   else
+	     $write("%d\t",adc_out);
+	   $write("%f\t",adc_in_del/factor);
+	   $write("%f\n",adc_in_del/factor-adc_out);
+	end	
+   
+   round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT)) 
+   round_sd(.clk(clk),.reset(rst), .in(adc_in),.out(adc_out));
+
+   always @(posedge clk)
+     adc_in <= 4734;
+     //adc_in <= $random % 4739;
+
+   always @(posedge clk)
+     adc_in_del <= adc_in;
+
+   initial #10000 $finish;
+   
+endmodule // longfifo_tb
-- 
cgit v1.2.3


From 569d9ee60153ac129aa275ca43688c3b94eb8c84 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 4 Apr 2011 21:41:41 -0700
Subject: dsp: reworked round_sd, it is much simpler now

---
 usrp2/sdr_lib/round_sd.v    | 40 +++++++++-------------------------------
 usrp2/sdr_lib/round_sd_tb.v |  8 +++++---
 2 files changed, 14 insertions(+), 34 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/round_sd.v b/usrp2/sdr_lib/round_sd.v
index 9c2a69615..b77c1471b 100644
--- a/usrp2/sdr_lib/round_sd.v
+++ b/usrp2/sdr_lib/round_sd.v
@@ -6,38 +6,16 @@ module round_sd
    (input clk, input reset,
     input [WIDTH_IN-1:0] in, output [WIDTH_OUT-1:0] out);
 
-   localparam SUM_WIDTH = WIDTH_IN+1;
-   localparam ERR_WIDTH = SUM_WIDTH - (WIDTH_OUT + 1) + 1;
-   localparam ACC_WIDTH = ERR_WIDTH + 1;
-   
-   reg [ACC_WIDTH-1:0] 	 acc;
-   wire [SUM_WIDTH-1:0] acc_ext, in_ext;
-
-   sign_extend #(.bits_in(WIDTH_IN),.bits_out(SUM_WIDTH)) ext_in (.in(in), .out(in_ext));
-   sign_extend #(.bits_in(ACC_WIDTH),.bits_out(SUM_WIDTH)) ext_acc (.in(acc), .out(acc_ext));
-   
-   wire [SUM_WIDTH-1:0] sum = in_ext + acc_ext;
-   wire [WIDTH_OUT:0] 	sum_round;
-   wire [ERR_WIDTH-1:0] err;
-   wire [ACC_WIDTH-1:0] err_ext;
-   
-   //round_reg #(.bits_in(SUM_WIDTH),.bits_out(WIDTH_OUT+1))  round_sum (.clk(clk), .in(sum), .out(sum_round));
-   round #(.bits_in(SUM_WIDTH),.bits_out(WIDTH_OUT+1))  round_sum ( .in(sum), .out(sum_round));
+   localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1;
 
-   reg [WIDTH_IN-1:0] 	in_del;
-   always @(posedge clk)
-     in_del <= in;
-   
-   assign err = in_del - {sum_round,{SUM_WIDTH-WIDTH_OUT-1{1'b0}}};
+   wire [ERR_WIDTH-1:0]  err;
+   wire [WIDTH_IN-1:0] 	 err_ext, sum;
+  
+   sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext));
    
-   clip #(.bits_in(WIDTH_OUT+1),.bits_out(WIDTH_OUT)) clip (.in(sum_round), .out(out));
-
-   sign_extend #(.bits_in(ERR_WIDTH),.bits_out(ACC_WIDTH)) ext_err (.in(err), .out(err_ext));
+   add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg
+     (.clk(clk), .rst(reset), .in1(in), .in2(err_ext), .sum(sum));
    
-   always @(posedge clk)
-     if(reset)
-       acc <= 0;
-     else
-       acc <= acc + err_ext;
+   round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err));
    
-endmodule // rx_dcoffset
+endmodule // round_sd
diff --git a/usrp2/sdr_lib/round_sd_tb.v b/usrp2/sdr_lib/round_sd_tb.v
index df9f58421..80b3707dc 100644
--- a/usrp2/sdr_lib/round_sd_tb.v
+++ b/usrp2/sdr_lib/round_sd_tb.v
@@ -30,15 +30,17 @@ module round_sd_tb();
 	     $write("-%d\t",-adc_out);
 	   else
 	     $write("%d\t",adc_out);
-	   $write("%f\t",adc_in_del/factor);
-	   $write("%f\n",adc_in_del/factor-adc_out);
+	   $write("\n");
+	   
+	   //$write("%f\t",adc_in_del/factor);
+	   //$write("%f\n",adc_in_del/factor-adc_out);
 	end	
    
    round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT)) 
    round_sd(.clk(clk),.reset(rst), .in(adc_in),.out(adc_out));
 
    always @(posedge clk)
-     adc_in <= 4734;
+     adc_in <= 14'h1FDF;
      //adc_in <= $random % 4739;
 
    always @(posedge clk)
-- 
cgit v1.2.3


From 7b127e2f51f636baf1d39f46cc9afd09579bf74f Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 18 Apr 2011 13:59:43 -0700
Subject: dsp: use sigma delta rounding in rx_dcoffset and in dsp_core_rx

---
 usrp2/sdr_lib/dsp_core_rx.v |  4 ++--
 usrp2/sdr_lib/rx_dcoffset.v | 18 ++++--------------
 2 files changed, 6 insertions(+), 16 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index ae6cdbdf3..f17c2816f 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -102,8 +102,8 @@ module dsp_core_rx
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
 	      .signal_in(q_cordic),.signal_out(q_cic));
 
-   round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
-   round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
    reg 	       strobe_cic_d1;
    always @(posedge clk) strobe_cic_d1 <= strobe_cic;
    
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 52f8cd5be..97923b9bf 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -32,7 +32,8 @@ module rx_dcoffset
 
    localparam int_width = WIDTH + alpha_shift;
    reg [int_width-1:0] integrator;
-   
+   wire [WIDTH-1:0]    quantized;
+
    always @(posedge clk)
      if(rst)
        begin
@@ -47,19 +48,8 @@ module rx_dcoffset
      else if(~fixed)
        integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
 
-   wire [WIDTH-1:0] quantized;
-   wire [int_width-WIDTH:0] q_err;
-   wire [int_width-1:0]     q_err_ext;
-   wire [int_width-1:0]     q_loop;
-
-   round #(.bits_in(int_width), .bits_out(WIDTH)) quantizer
-     (.in(q_loop), .out(quantized), .err(q_err));
-   
-   sign_extend #(.bits_in(int_width-WIDTH+1),.bits_out(int_width)) sign_extend
-     (.in(q_err), .out(q_err_ext));
-   
-   add2_and_clip_reg #(.WIDTH(int_width)) sd_fixed
-     (.clk(clk), .rst(rst), .in1(integrator), .in2(q_err_ext), .sum(q_loop));
+   round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
+     (.clk(clk), .reset(rst), .in(integrator), .out(quantized));
    
    add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
      (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .sum(out));
-- 
cgit v1.2.3


From 90c74cd45885ab2aba3d090a8deebd11b96c6d7c Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 18 Apr 2011 14:13:50 -0700
Subject: u2/u2p: use new rx_frontend in u2 and u2p

---
 usrp2/sdr_lib/rx_frontend.v  |  4 ++--
 usrp2/top/N2x0/u2plus_core.v | 15 +++++++++++++--
 usrp2/top/USRP2/u2_core.v    |  4 ++--
 3 files changed, 17 insertions(+), 6 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index 3b05a4a08..0ad83f6c7 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -69,7 +69,7 @@ module rx_frontend
      (.clk(clk), .rst(rst), 
       .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final));
 
-   assign i_out = i_final[23:6];
-   assign q_out = q_final[23:6];
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i (.clk(clk), .reset(rst), .in(i_final), .out(i_out));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q (.clk(clk), .reset(rst), .in(q_final), .out(q_out));
    
 endmodule // rx_frontend
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 8a7c6ddee..3d67b0dcf 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -583,6 +583,17 @@ module u2plus_core
       .ss_pad_o(spiflash_cs),
       .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) );
 
+   // /////////////////////////////////////////////////////////////////////////
+   // ADC Frontend
+   wire [17:0] 	 adc_i, adc_q;
+   
+   rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a),
+      .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b),
+      .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug());
+   
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 0
    wire [31:0] 	 sample_rx0;
@@ -594,7 +605,7 @@ module u2plus_core
    dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),
       .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
       .debug() );
 
@@ -622,7 +633,7 @@ module u2plus_core
    dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),
       .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
       .debug() );
 
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 151ac27ae..0821277cc 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -283,7 +283,7 @@ module u2_core
       .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
       .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
       
-   //////////////////////////////////////////////////////////////////////////////////////////
+   // ////////////////////////////////////////////////////////////////////////////////////////
    // Reset Controller
    system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
 			   .ram_loader_rst_o(ram_loader_rst),
@@ -586,7 +586,7 @@ module u2_core
    // ADC Frontend
    wire [17:0] 	 adc_i, adc_q;
    
-   rx_frontend #(.BASE()) rx_frontend
+   rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a),
-- 
cgit v1.2.3


From 568535308d377eeb459a385f7a10b40cbe73a4d9 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 9 May 2011 17:20:32 -0700
Subject: dsp: add2_and_clip_reg and round_sd now are now strobed to be
 compatible with strobed (non-full rate) data

---
 usrp2/sdr_lib/add2_and_clip_reg.v |  9 +++++++--
 usrp2/sdr_lib/dsp_core_rx.v       | 20 +++++++++++---------
 usrp2/sdr_lib/round_sd.v          |  5 +++--
 usrp2/sdr_lib/round_sd_tb.v       | 21 ++++++++++++++-------
 usrp2/sdr_lib/rx_dcoffset.v       |  4 ++--
 usrp2/sdr_lib/rx_frontend.v       | 13 +++++++++----
 6 files changed, 46 insertions(+), 26 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/add2_and_clip_reg.v b/usrp2/sdr_lib/add2_and_clip_reg.v
index 7070f1cea..8073b3b54 100644
--- a/usrp2/sdr_lib/add2_and_clip_reg.v
+++ b/usrp2/sdr_lib/add2_and_clip_reg.v
@@ -5,7 +5,9 @@ module add2_and_clip_reg
      input rst,
      input [WIDTH-1:0] in1,
      input [WIDTH-1:0] in2,
-     output reg [WIDTH-1:0] sum);
+     input strobe_in,
+     output reg [WIDTH-1:0] sum,
+     output reg strobe_out);
 
    wire [WIDTH-1:0] sum_int;
    
@@ -14,7 +16,10 @@ module add2_and_clip_reg
    always @(posedge clk)
      if(rst)
        sum <= 0;
-     else
+     else if(strobe_in)
        sum <= sum_int;
+
+   always @(posedge clk)
+     strobe_out <= strobe_in;
    
 endmodule // add2_and_clip_reg
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index f17c2816f..6a12836f2 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -102,10 +102,12 @@ module dsp_core_rx
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
 	      .signal_in(q_cordic),.signal_out(q_cic));
 
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
-   reg 	       strobe_cic_d1;
-   always @(posedge clk) strobe_cic_d1 <= strobe_cic;
+   wire        strobe_cic_d1;
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_icic (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1));
+   
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_qcic (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out());
    
    small_hb_dec #(.WIDTH(18)) small_hb_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
@@ -124,13 +126,13 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
-   round_reg #(.bits_in(18),.bits_out(16)) round_iout (.clk(clk),.in(i_hb2),.out(i_out));
-   round_reg #(.bits_in(18),.bits_out(16)) round_qout (.clk(clk),.in(q_hb2),.out(q_out));
-   reg 	       strobe_out;
-   always @(posedge clk) strobe_out <= strobe_hb2;
+   round_sd #(.bits_in(18),.bits_out(16)) 
+   round_iout (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
+   
+   round_sd #(.bits_in(18),.bits_out(16)) 
+   round_qout (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
    
    assign      sample = {i_hb2,q_hb2};
-   assign      strobe = strobe_out;
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
    
 endmodule // dsp_core_rx
diff --git a/usrp2/sdr_lib/round_sd.v b/usrp2/sdr_lib/round_sd.v
index b77c1471b..aeeb3502f 100644
--- a/usrp2/sdr_lib/round_sd.v
+++ b/usrp2/sdr_lib/round_sd.v
@@ -4,7 +4,8 @@ module round_sd
   #(parameter WIDTH_IN=18,
     parameter WIDTH_OUT=16)
    (input clk, input reset,
-    input [WIDTH_IN-1:0] in, output [WIDTH_OUT-1:0] out);
+    input [WIDTH_IN-1:0] in, input strobe_in,
+    output [WIDTH_OUT-1:0] out, output strobe_out);
 
    localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1;
 
@@ -14,7 +15,7 @@ module round_sd
    sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext));
    
    add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg
-     (.clk(clk), .rst(reset), .in1(in), .in2(err_ext), .sum(sum));
+     (.clk(clk), .rst(reset), .in1(in), .in2(err_ext), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_out));
    
    round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err));
    
diff --git a/usrp2/sdr_lib/round_sd_tb.v b/usrp2/sdr_lib/round_sd_tb.v
index 80b3707dc..1e8e9a323 100644
--- a/usrp2/sdr_lib/round_sd_tb.v
+++ b/usrp2/sdr_lib/round_sd_tb.v
@@ -11,8 +11,8 @@ module round_sd_tb();
    initial $dumpfile("round_sd_tb.vcd");
    initial $dumpvars(0,round_sd_tb);
 
-   localparam WIDTH_IN = 14;
-   localparam WIDTH_OUT = 10;
+   localparam WIDTH_IN = 8;
+   localparam WIDTH_OUT = 5;
    
    reg [WIDTH_IN-1:0] adc_in, adc_in_del;
    wire [WIDTH_OUT-1:0] adc_out;
@@ -37,15 +37,22 @@ module round_sd_tb();
 	end	
    
    round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT)) 
-   round_sd(.clk(clk),.reset(rst), .in(adc_in),.out(adc_out));
+   round_sd(.clk(clk),.reset(rst), .in(adc_in), .strobe_in(1'b1), .out(adc_out), .strobe_out());
 
+   reg [5:0] counter = 0;
+   
    always @(posedge clk)
-     adc_in <= 14'h1FDF;
-     //adc_in <= $random % 4739;
-
+     counter <= counter+1;
+   
    always @(posedge clk)
      adc_in_del <= adc_in;
 
-   initial #10000 $finish;
+   always @(posedge clk)
+     if(rst)
+       adc_in <= 0;
+     else if(counter == 63)
+       adc_in <= adc_in + 1;
+   
+   initial #300000 $finish;
    
 endmodule // longfifo_tb
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 97923b9bf..350579056 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -49,9 +49,9 @@ module rx_dcoffset
        integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
 
    round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
-     (.clk(clk), .reset(rst), .in(integrator), .out(quantized));
+     (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), strobe_out());
    
    add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
-     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .sum(out));
+     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), strobe_out());
 
 endmodule // rx_dcoffset
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index 0ad83f6c7..98f72509c 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -63,13 +63,18 @@ module rx_frontend
    
    add2_and_clip_reg #(.WIDTH(24)) add_clip_i
      (.clk(clk), .rst(rst), 
-      .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final));
+      .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), 
+      .sum(i_final), .strobe_out());
    
    add2_and_clip_reg #(.WIDTH(24)) add_clip_q
      (.clk(clk), .rst(rst), 
-      .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final));
+      .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1),
+      .sum(q_final), .strobe_out());
 
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i (.clk(clk), .reset(rst), .in(i_final), .out(i_out));
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q (.clk(clk), .reset(rst), .in(q_final), .out(q_out));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_i (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out());
+   
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_q (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out());
    
 endmodule // rx_frontend
-- 
cgit v1.2.3


From 2e2de3f8f7e055c9f583a17a513774f307ffbc04 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 9 May 2011 17:28:54 -0700
Subject: dsp: fix typos

---
 usrp2/sdr_lib/dsp_core_rx.v | 16 ++++++++--------
 usrp2/sdr_lib/rx_dcoffset.v |  4 ++--
 usrp2/sdr_lib/rx_frontend.v |  8 ++++----
 3 files changed, 14 insertions(+), 14 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 6a12836f2..8c8297124 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -103,11 +103,11 @@ module dsp_core_rx
 	      .signal_in(q_cordic),.signal_out(q_cic));
 
    wire        strobe_cic_d1;
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
-   round_icic (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic
+     (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1));
    
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
-   round_qcic (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out());
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic
+     (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out());
    
    small_hb_dec #(.WIDTH(18)) small_hb_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
@@ -126,11 +126,11 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
-   round_sd #(.bits_in(18),.bits_out(16)) 
-   round_iout (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
+   round_sd #(.bits_in(18),.bits_out(16)) round_iout
+     (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
    
-   round_sd #(.bits_in(18),.bits_out(16)) 
-   round_qout (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
+   round_sd #(.bits_in(18),.bits_out(16)) round_qout
+     (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
    
    assign      sample = {i_hb2,q_hb2};
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 350579056..e43461261 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -49,9 +49,9 @@ module rx_dcoffset
        integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
 
    round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
-     (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), strobe_out());
+     (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), .strobe_out());
    
    add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
-     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), strobe_out());
+     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), .strobe_out());
 
 endmodule // rx_dcoffset
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index 98f72509c..f93172f16 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -71,10 +71,10 @@ module rx_frontend
       .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1),
       .sum(q_final), .strobe_out());
 
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
-   round_i (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out());
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i
+     (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out());
    
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
-   round_q (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out());
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q
+     (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out());
    
 endmodule // rx_frontend
-- 
cgit v1.2.3


From e78a301ed17bbb79d688b21a72fa839eeb98aa9a Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 9 May 2011 17:31:41 -0700
Subject: dsp: new files in dsp directory

---
 usrp2/sdr_lib/Makefile.srcs | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/Makefile.srcs b/usrp2/sdr_lib/Makefile.srcs
index 4a85726a9..6dab1db5e 100644
--- a/usrp2/sdr_lib/Makefile.srcs
+++ b/usrp2/sdr_lib/Makefile.srcs
@@ -8,6 +8,8 @@
 SDR_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../sdr_lib/, \
 acc.v \
 add2.v \
+add2_and_clip.v \
+add2_and_clip_reg.v \
 add2_and_round.v \
 add2_and_round_reg.v \
 add2_reg.v \
@@ -28,6 +30,7 @@ hb_dec.v \
 hb_interp.v \
 round.v \
 round_reg.v \
+round_sd.v \
 rx_control.v \
 rx_dcoffset.v \
 rx_frontend.v \
-- 
cgit v1.2.3


From 757d06d2f3393a4ef6c85b610419c6e4922709bb Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 9 May 2011 17:35:08 -0700
Subject: dsp: more typos

---
 usrp2/sdr_lib/dsp_core_rx.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 8c8297124..afba3428e 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -126,10 +126,10 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
-   round_sd #(.bits_in(18),.bits_out(16)) round_iout
+   round_sd #(.WIDTH_IN(18),.WIDTH_OUT(16)) round_iout
      (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
    
-   round_sd #(.bits_in(18),.bits_out(16)) round_qout
+   round_sd #(.WIDTH_IN(18),.WIDTH_OUT(16)) round_qout
      (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
    
    assign      sample = {i_hb2,q_hb2};
-- 
cgit v1.2.3


From 3993b882c9f3aa69b1cdb6e7370bedd6d9e7931a Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 11 May 2011 17:57:45 -0700
Subject: dsp: reworked muxes on rx

---
 usrp2/sdr_lib/dsp_core_rx.v | 24 ++++++++++++++++++++++--
 usrp2/sdr_lib/rx_frontend.v | 29 +++++++++--------------------
 2 files changed, 31 insertions(+), 22 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index afba3428e..1b04c4f36 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -46,6 +46,10 @@ module dsp_core_rx
    wire        enable_hb1, enable_hb2;
    wire [7:0]  cic_decim_rate;
 
+   reg [17:0]  adc_i_mux, adc_q_mux;
+   wire        realmode;
+   wire        swap_iq;
+   
    setting_reg #(.my_addr(BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
@@ -58,6 +62,22 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
 
+   setting_reg #(.my_addr(BASE+3), .width(2)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({realmode,swap_iq}),.changed());
+
+   always @(posedge clk)
+     if(swap_iq)
+       begin
+	  adc_i_mux <= adc_q;
+	  adc_q_mux <= realmode ? 18'd0 : adc_i;
+       end
+     else
+       begin
+	  adc_i_mux <= adc_i;
+	  adc_q_mux <= realmode ? 18'd0 : adc_q;
+       end
+   
    always @(posedge clk)
      if(rst)
        phase <= 0;
@@ -68,7 +88,7 @@ module dsp_core_rx
 
    MULT18X18S mult_i
      (.P(prod_i),    // 36-bit multiplier output
-      .A(adc_i),    // 18-bit multiplier input
+      .A(adc_i_mux),    // 18-bit multiplier input
       .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input
@@ -77,7 +97,7 @@ module dsp_core_rx
 
    MULT18X18S mult_q
      (.P(prod_q),    // 36-bit multiplier output
-      .A(adc_q),    // 18-bit multiplier input
+      .A(adc_q_mux),    // 18-bit multiplier input
       .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index f93172f16..a95110240 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -14,31 +14,20 @@ module rx_frontend
    
    reg [15:0] 	  adc_i, adc_q;
    wire [17:0] 	  adc_i_ofs, adc_q_ofs;
-   wire [35:0] 	  corr_i, corr_q;
-   wire [17:0] 	  mag_corr,phase_corr;
-   wire [7:0] 	  muxctrl;
+   wire [35:0] 	  corr_i, corr_q; wire [17:0] 	  mag_corr,phase_corr;
+   wire 	  swap_iq;
    wire [23:0] 	  i_final, q_final;
    
-   setting_reg #(.my_addr(BASE), .width(8)) sr_8
+   setting_reg #(.my_addr(BASE), .width(1)) sr_8
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(muxctrl),.changed());
+      .in(set_data),.out(swap_iq),.changed());
 
    always @(posedge clk)
-     case(muxctrl[3:0])		// The I mapping
-       0: adc_i <= adc_a;
-       1: adc_i <= adc_b;
-       2: adc_i <= 0;
-       default: adc_i <= 0;
-     endcase // case (muxctrl[3:0])
-   
-   always @(posedge clk)
-     case(muxctrl[7:4])		// The Q mapping
-       0: adc_q <= adc_a;
-       1: adc_q <= adc_b;
-       2: adc_q <= 0;
-       default: adc_q <= 0;
-     endcase // case (muxctrl[7:4])
-   
+     if(swap_iq) // Swap
+       {adc_i,adc_q} <= {adc_b,adc_a};
+     else
+       {adc_i,adc_q} <= {adc_a,adc_b};
+       
    setting_reg #(.my_addr(BASE+1),.width(18)) sr_1
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(mag_corr),.changed());
-- 
cgit v1.2.3


From 2edca948d0a43159138b3754c49a26e0dae562a1 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 12 May 2011 16:29:41 -0700
Subject: dsp: do proper rounding at the end of dsp chain

---
 usrp2/sdr_lib/dsp_core_rx.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 1b04c4f36..cd3e7cc22 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -152,7 +152,7 @@ module dsp_core_rx
    round_sd #(.WIDTH_IN(18),.WIDTH_OUT(16)) round_qout
      (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
    
-   assign      sample = {i_hb2,q_hb2};
+   assign      sample = {i_out,q_out};
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
    
 endmodule // dsp_core_rx
-- 
cgit v1.2.3


From 3a4e028a9e96109f4bfacce48b15349833b9e229 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 12 May 2011 21:18:25 -0700
Subject: dsp: add resets for simulation purposes

---
 usrp2/sdr_lib/dsp_core_rx.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index cd3e7cc22..ca1e0d5b4 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -124,10 +124,10 @@ module dsp_core_rx
 
    wire        strobe_cic_d1;
    round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic
-     (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1));
+     (.clk(clk),.reset(rst), .in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1));
    
    round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic
-     (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out());
+     (.clk(clk),.reset(rst), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out());
    
    small_hb_dec #(.WIDTH(18)) small_hb_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
@@ -147,10 +147,10 @@ module dsp_core_rx
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
    round_sd #(.WIDTH_IN(18),.WIDTH_OUT(16)) round_iout
-     (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
+     (.clk(clk), .reset(rst), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
    
    round_sd #(.WIDTH_IN(18),.WIDTH_OUT(16)) round_qout
-     (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
+     (.clk(clk), .reset(rst), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
    
    assign      sample = {i_out,q_out};
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
-- 
cgit v1.2.3


From f21bc7eea8044ca89a39be4afd8eb591996d14fe Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 12 May 2011 21:20:01 -0700
Subject: dsp: tx_dcoffset, not integrated yet

---
 usrp2/sdr_lib/tx_dcoffset.v | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 usrp2/sdr_lib/tx_dcoffset.v

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/tx_dcoffset.v b/usrp2/sdr_lib/tx_dcoffset.v
new file mode 100644
index 000000000..737693611
--- /dev/null
+++ b/usrp2/sdr_lib/tx_dcoffset.v
@@ -0,0 +1,26 @@
+
+// TX DC offset.  Setting is 8 fractional bits, 8 integer bits
+
+module tx_dcoffset 
+  #(parameter WIDTH_IN=16,
+    parameter WIDTH_OUT=16,
+    parameter ADDR=8'd0)
+   (input clk, input rst, 
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [WIDTH_IN-1:0] in, output [WIDTH_OUT-1:0] out);
+
+   wire [15:0] 		 dco;
+   wire [WIDTH_IN+8-1:0] dco_ext, sum;
+ 
+   setting_reg #(.my_addr(ADDR),.width(16)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(dco));
+   
+   sign_extend #(.bits_in(16),.bits_out(WIDTH_IN+8)) ext_err (.in(dco), .out(dco_ext));
+ 
+   add2_and_clip_reg #(.WIDTH(WIDTH_IN+8)) add2_and_clip_reg
+     (.clk(clk), .rst(rst), .in1({in,8'd0}), .in2(dco_ext), .strobe_in(1'b1), .sum(sum), .strobe_out());
+
+   round_sd #(.WIDTH_IN(WIDTH_IN+8),.WIDTH_OUT(WIDTH_OUT)) round_sd
+     (.clk(clk), .reset(rst), .in(sum), .strobe_in(1'b1), .out(out), .strobe_out());
+   
+endmodule // rx_dcoffset
-- 
cgit v1.2.3


From 554d08aeaebabbc619b4b790d0c7788fc798cb12 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 12 May 2011 21:20:36 -0700
Subject: dsp: testbenches for dsp blocks

---
 usrp2/sdr_lib/dsp_core_rx_tb.v | 68 ++++++++++++++++++++++++++++++++++++++++++
 usrp2/sdr_lib/rx_frontend_tb.v | 45 ++++++++++++++++++++++++++++
 2 files changed, 113 insertions(+)
 create mode 100644 usrp2/sdr_lib/dsp_core_rx_tb.v
 create mode 100644 usrp2/sdr_lib/rx_frontend_tb.v

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx_tb.v b/usrp2/sdr_lib/dsp_core_rx_tb.v
new file mode 100644
index 000000000..991b3a850
--- /dev/null
+++ b/usrp2/sdr_lib/dsp_core_rx_tb.v
@@ -0,0 +1,68 @@
+
+`timescale 1ns/1ns
+module dsp_core_rx_tb();
+   
+   reg clk, rst;
+
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #5 clk = ~clk;
+   
+   initial $dumpfile("dsp_core_rx_tb.vcd");
+   initial $dumpvars(0,dsp_core_rx_tb);
+   
+   reg [17:0] adc_in;
+   wire [15:0] adc_out_i, adc_out_q;
+
+   always @(posedge clk)
+     begin
+	if(adc_in[17])
+	  $write("-%d,",-adc_in);
+	else
+	  $write("%d,",adc_in);
+	if(adc_out_i[15])
+	  $write("-%d\n",-adc_out_i);
+	else
+	  $write("%d\n",adc_out_i);
+     end	
+
+   reg run;
+   reg set_stb;
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+   
+   dsp_core_rx #(.BASE(0)) dsp_core_rx
+     (.clk(clk),.rst(rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_i(adc_in), .adc_ovf_i(0),
+      .adc_q(0), .adc_ovf_q(0),
+      .sample({adc_out_i,adc_out_q}),
+      .run(run), .strobe(), .debug());
+
+   initial
+     begin
+	run <= 0;
+	@(negedge rst);
+	@(posedge clk);
+	set_addr <= 1;
+	set_data <= {16'd1024,16'd1024};
+	set_stb <= 1;
+	@(posedge clk);
+	set_addr <= 2;
+	set_data <= 8;
+	set_stb <= 1;
+	@(posedge clk);
+	set_stb <= 0;
+	@(posedge clk);
+	run <= 1;
+     end
+   
+   always @(posedge clk)
+     if(rst)
+       adc_in <= 0;
+     else
+       adc_in <= adc_in + 4;
+   //adc_in <= (($random % 473) + 23)/4;
+   
+endmodule // dsp_core_rx_tb
diff --git a/usrp2/sdr_lib/rx_frontend_tb.v b/usrp2/sdr_lib/rx_frontend_tb.v
new file mode 100644
index 000000000..487b72687
--- /dev/null
+++ b/usrp2/sdr_lib/rx_frontend_tb.v
@@ -0,0 +1,45 @@
+
+`timescale 1ns/1ns
+module rx_frontend_tb();
+   
+   reg clk, rst;
+
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #5 clk = ~clk;
+   
+   initial $dumpfile("rx_frontend_tb.vcd");
+   initial $dumpvars(0,rx_frontend_tb);
+
+   reg [15:0] adc_in;
+   wire [17:0] adc_out;
+
+   always @(posedge clk)
+     begin
+	if(adc_in[13])
+	  $write("-%d,",-adc_in);
+	else
+	  $write("%d,",adc_in);
+	if(adc_out[13])
+	  $write("-%d\n",-adc_out);
+	else
+	  $write("%d\n",adc_out);
+     end	
+   
+   rx_frontend #(.BASE(0)) rx_frontend
+     (.clk(clk),.rst(rst),
+      .set_stb(0),.set_addr(0),.set_data(0),
+      .adc_a(adc_in), .adc_ovf_a(0),
+      .adc_b(0), .adc_ovf_b(0),
+      .i_out(adc_out),.q_out(),
+      .run(), .debug());
+
+   always @(posedge clk)
+     if(rst)
+       adc_in <= 0;
+     else
+       adc_in <= adc_in + 4;
+   //adc_in <= (($random % 473) + 23)/4;
+   
+endmodule // rx_frontend_tb
-- 
cgit v1.2.3


From f2ea250dc491c284bbfa895c79a44e5f4f34c484 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 12 May 2011 23:43:19 -0700
Subject: dsp: reorganized scaling and rounding, removed multipliers (will put
 back in a different location)

---
 usrp2/sdr_lib/dsp_core_rx.v    | 56 ++++++++++++++++++++----------------------
 usrp2/sdr_lib/dsp_core_rx_tb.v |  4 +--
 usrp2/sdr_lib/hb_dec.v         | 35 +++++++++++++-------------
 3 files changed, 46 insertions(+), 49 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index ca1e0d5b4..19215c777 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -39,8 +39,7 @@ module dsp_core_rx
    wire [23:0] i_cic, q_cic;
    wire [17:0] i_cic_scaled, q_cic_scaled;
    wire [17:0] i_hb1, q_hb1;
-   wire [17:0] i_hb2, q_hb2;
-   wire [15:0] i_out, q_out;
+   wire [15:0] i_hb2, q_hb2;
 
    wire        strobe_cic, strobe_hb1, strobe_hb2;
    wire        enable_hb1, enable_hb2;
@@ -86,27 +85,9 @@ module dsp_core_rx
      else
        phase <= phase + phase_inc;
 
-   MULT18X18S mult_i
-     (.P(prod_i),    // 36-bit multiplier output
-      .A(adc_i_mux),    // 18-bit multiplier input
-      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
-      .C(clk),    // Clock input
-      .CE(1),  // Clock enable input
-      .R(rst)     // Synchronous reset input
-      );
-
-   MULT18X18S mult_q
-     (.P(prod_q),    // 36-bit multiplier output
-      .A(adc_q_mux),    // 18-bit multiplier input
-      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
-      .C(clk),    // Clock input
-      .CE(1),  // Clock enable input
-      .R(rst)     // Synchronous reset input
-      ); 
-   
    cordic_z24 #(.bitwidth(24))
      cordic(.clock(clk), .reset(rst), .enable(run),
-	    .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]),
+	    .xi({adc_i_mux,6'd0}),. yi({adc_q_mux,6'd0}), .zi(phase[31:8]),
 	    .xo(i_cordic),.yo(q_cordic),.zo() );
 
    cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
@@ -138,21 +119,38 @@ module dsp_core_rx
       .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1));
 
    wire [8:0]  cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
-   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i
+   hb_dec #(.IWIDTH(18), .OWIDTH(16), .CWIDTH(18), .ACCWIDTH(24)) hb_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
 
-   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q
+   hb_dec #(.IWIDTH(18), .OWIDTH(16), .CWIDTH(18), .ACCWIDTH(24)) hb_q
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
-   round_sd #(.WIDTH_IN(18),.WIDTH_OUT(16)) round_iout
-     (.clk(clk), .reset(rst), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
-   
-   round_sd #(.WIDTH_IN(18),.WIDTH_OUT(16)) round_qout
-     (.clk(clk), .reset(rst), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
+   assign      sample = {i_hb2,q_hb2};
+   assign      strobe = strobe_hb2;
    
-   assign      sample = {i_out,q_out};
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
    
 endmodule // dsp_core_rx
+
+/*
+   MULT18X18S mult_i
+     (.P(prod_i),    // 36-bit multiplier output
+      .A(adc_i_mux),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+
+   MULT18X18S mult_q
+     (.P(prod_q),    // 36-bit multiplier output
+      .A(adc_q_mux),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      ); 
+   
+*/
diff --git a/usrp2/sdr_lib/dsp_core_rx_tb.v b/usrp2/sdr_lib/dsp_core_rx_tb.v
index 991b3a850..c8fb33982 100644
--- a/usrp2/sdr_lib/dsp_core_rx_tb.v
+++ b/usrp2/sdr_lib/dsp_core_rx_tb.v
@@ -46,11 +46,11 @@ module dsp_core_rx_tb();
 	@(negedge rst);
 	@(posedge clk);
 	set_addr <= 1;
-	set_data <= {16'd1024,16'd1024};
+	set_data <= {16'd64,16'd64};
 	set_stb <= 1;
 	@(posedge clk);
 	set_addr <= 2;
-	set_data <= 8;
+	set_data <= {16'd0,8'd3,8'd8};
 	set_stb <= 1;
 	@(posedge clk);
 	set_stb <= 0;
diff --git a/usrp2/sdr_lib/hb_dec.v b/usrp2/sdr_lib/hb_dec.v
index 9747f0adb..59c66ea28 100644
--- a/usrp2/sdr_lib/hb_dec.v
+++ b/usrp2/sdr_lib/hb_dec.v
@@ -30,8 +30,8 @@ module hb_dec
      input [8:0] cpi,  // Clocks per input -- equal to the decimation ratio ahead of this block
      input stb_in,
      input [IWIDTH-1:0] data_in,
-     output reg stb_out,
-     output reg [OWIDTH-1:0] data_out);
+     output stb_out,
+     output [OWIDTH-1:0] data_out);
 
    // Control
    reg [3:0] 		addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d;
@@ -167,22 +167,21 @@ module hb_dec
    add2_reg /* add2_and_round_reg */ #(.WIDTH(ACCWIDTH+1)) 
      final_adder (.clk(clk), .in1({acc_out,1'b0}), .in2({data_even_signext,1'b0}), .sum(final_sum_unrounded));
 
-   round_reg #(.bits_in(ACCWIDTH-4),.bits_out(OWIDTH))
-     final_round (.clk(clk),.in(final_sum_unrounded[ACCWIDTH-5:0]),.out(final_sum));
+   wire [OWIDTH-1:0] 	bypass_data;
+   wire 		stb_final, stb_bypass;
+   
+   round_sd #(.WIDTH_IN(ACCWIDTH-4),.WIDTH_OUT(OWIDTH))
+   final_round (.clk(clk),.reset(rst),
+		.in(final_sum_unrounded[ACCWIDTH-5:0]),.strobe_in(stb_out_pre[9]),
+		.out(final_sum), .strobe_out(stb_final));
 
-   // Output
-   always @(posedge clk)
-     if(bypass)
-       data_out <= data_in;
-     else if(stb_out_pre[9])
-       data_out <= final_sum;
+   round_sd #(.WIDTH_IN(IWIDTH),.WIDTH_OUT(OWIDTH))
+   bypass_round (.clk(clk),.reset(rst),
+		 .in(data_in),.strobe_in(stb_in),
+		 .out(bypass_data), .strobe_out(stb_bypass));
 
-   always @(posedge clk)
-     if(rst)
-       stb_out <= 0;
-     else if(bypass)
-       stb_out <= stb_in;
-     else
-       stb_out <= stb_out_pre[9];
- 
+   // Output
+   assign stb_out = bypass ? stb_bypass : stb_final;
+   assign data_out = bypass ? bypass_data : final_sum;
+   
 endmodule // hb_dec
-- 
cgit v1.2.3


From e0654430583fb4980165adbcfd04aa9bf04c429b Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 13 May 2011 12:47:52 -0700
Subject: dsp: use round_sd in small_hb_dec

---
 usrp2/sdr_lib/small_hb_dec.v | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/small_hb_dec.v b/usrp2/sdr_lib/small_hb_dec.v
index 151b8c287..ecafc2b68 100644
--- a/usrp2/sdr_lib/small_hb_dec.v
+++ b/usrp2/sdr_lib/small_hb_dec.v
@@ -107,13 +107,16 @@ module small_hb_dec
        accum <= accum + {prod};
    
    wire [17:0] 	 accum_rnd;
-   round #(.bits_in(36),.bits_out(18)) round_acc (.in(accum),.out(accum_rnd));
+   wire 	 stb_round;
+   
+   round_sd #(.WIDTH_IN(36),.WIDTH_OUT(18)) round_acc 
+     (.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round));
 
    reg [17:0] 	 final_sum;
    always @(posedge clk)
      if(bypass)
        final_sum <= data_in_d1;
-     else if(go_d4)
+     else if(stb_round)
        final_sum <= accum_rnd;
 
    assign 	 data_out = final_sum;
@@ -124,5 +127,5 @@ module small_hb_dec
      else if(bypass)
        stb_out <= stb_in_d1;
      else
-       stb_out <= go_d4;
+       stb_out <= stb_round;
 endmodule // small_hb_dec
-- 
cgit v1.2.3


From d35bbdf5a68dd8227354b4352043867f43b20b09 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 13 May 2011 13:06:16 -0700
Subject: dsp: increase gain of small_hb_dec because it used to scale down by
 factor of 2.  Clip if needed.

---
 usrp2/sdr_lib/dsp_core_rx_tb.v |  4 ++--
 usrp2/sdr_lib/small_hb_dec.v   | 10 +++++++---
 2 files changed, 9 insertions(+), 5 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx_tb.v b/usrp2/sdr_lib/dsp_core_rx_tb.v
index c8fb33982..ff35d4027 100644
--- a/usrp2/sdr_lib/dsp_core_rx_tb.v
+++ b/usrp2/sdr_lib/dsp_core_rx_tb.v
@@ -46,11 +46,11 @@ module dsp_core_rx_tb();
 	@(negedge rst);
 	@(posedge clk);
 	set_addr <= 1;
-	set_data <= {16'd64,16'd64};
+	set_data <= {16'd64,16'd64};  // set gains
 	set_stb <= 1;
 	@(posedge clk);
 	set_addr <= 2;
-	set_data <= {16'd0,8'd3,8'd8};
+	set_data <= {16'd0,8'd0,8'd8}; // set decim
 	set_stb <= 1;
 	@(posedge clk);
 	set_stb <= 0;
diff --git a/usrp2/sdr_lib/small_hb_dec.v b/usrp2/sdr_lib/small_hb_dec.v
index ecafc2b68..14e6d755c 100644
--- a/usrp2/sdr_lib/small_hb_dec.v
+++ b/usrp2/sdr_lib/small_hb_dec.v
@@ -106,18 +106,22 @@ module small_hb_dec
      else if(go_d3)
        accum <= accum + {prod};
    
-   wire [17:0] 	 accum_rnd;
+   wire [18:0] 	 accum_rnd;
+   wire [17:0] 	 accum_rnd_clip;
+   
    wire 	 stb_round;
    
-   round_sd #(.WIDTH_IN(36),.WIDTH_OUT(18)) round_acc 
+   round_sd #(.WIDTH_IN(36),.WIDTH_OUT(19)) round_acc 
      (.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round));
 
+   clip #(.bits_in(19),.bits_out(18)) clip (.in(accum_rnd), .out(accum_rnd_clip));
+   
    reg [17:0] 	 final_sum;
    always @(posedge clk)
      if(bypass)
        final_sum <= data_in_d1;
      else if(stb_round)
-       final_sum <= accum_rnd;
+       final_sum <= accum_rnd_clip;
 
    assign 	 data_out = final_sum;
 
-- 
cgit v1.2.3


From b9b183315a232b3bdd2c82ee924678612ff50e0c Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 13 May 2011 14:05:04 -0700
Subject: dsp: no need to keep all the low order bits from the accumulator

---
 usrp2/sdr_lib/small_hb_dec.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/small_hb_dec.v b/usrp2/sdr_lib/small_hb_dec.v
index 14e6d755c..41ecd3e41 100644
--- a/usrp2/sdr_lib/small_hb_dec.v
+++ b/usrp2/sdr_lib/small_hb_dec.v
@@ -111,8 +111,8 @@ module small_hb_dec
    
    wire 	 stb_round;
    
-   round_sd #(.WIDTH_IN(36),.WIDTH_OUT(19)) round_acc 
-     (.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round));
+   round_sd #(.WIDTH_IN(25),.WIDTH_OUT(19)) round_acc 
+     (.clk(clk), .reset(rst), .in(accum[35:11]), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round));
 
    clip #(.bits_in(19),.bits_out(18)) clip (.in(accum_rnd), .out(accum_rnd_clip));
    
-- 
cgit v1.2.3


From b5283ddff6ea1564688b0db83bcb98c1b195f698 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Sun, 15 May 2011 13:55:45 -0700
Subject: dsp: register hb output

---
 usrp2/sdr_lib/dsp_core_rx_tb.v |   2 +-
 usrp2/sdr_lib/hb_dec.v         |  17 ++-
 usrp2/sdr_lib/hb_dec_tb.v      |   6 +-
 usrp2/sdr_lib/input.dat        | 283 +----------------------------------------
 4 files changed, 15 insertions(+), 293 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx_tb.v b/usrp2/sdr_lib/dsp_core_rx_tb.v
index ff35d4027..67a558d55 100644
--- a/usrp2/sdr_lib/dsp_core_rx_tb.v
+++ b/usrp2/sdr_lib/dsp_core_rx_tb.v
@@ -50,7 +50,7 @@ module dsp_core_rx_tb();
 	set_stb <= 1;
 	@(posedge clk);
 	set_addr <= 2;
-	set_data <= {16'd0,8'd0,8'd8}; // set decim
+	set_data <= {16'd0,8'd3,8'd1}; // set decim
 	set_stb <= 1;
 	@(posedge clk);
 	set_stb <= 0;
diff --git a/usrp2/sdr_lib/hb_dec.v b/usrp2/sdr_lib/hb_dec.v
index 59c66ea28..eba79b938 100644
--- a/usrp2/sdr_lib/hb_dec.v
+++ b/usrp2/sdr_lib/hb_dec.v
@@ -30,8 +30,8 @@ module hb_dec
      input [8:0] cpi,  // Clocks per input -- equal to the decimation ratio ahead of this block
      input stb_in,
      input [IWIDTH-1:0] data_in,
-     output stb_out,
-     output [OWIDTH-1:0] data_out);
+     output reg stb_out,
+     output reg [OWIDTH-1:0] data_out);
 
    // Control
    reg [3:0] 		addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d;
@@ -126,8 +126,8 @@ module hb_dec
    srl #(.WIDTH(IWIDTH)) srl_odd_d
      (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_d),.out(data_odd_d));
 
-   add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1));
-   add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2));
+   add2_reg #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1));
+   add2_reg #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2));
 
    wire [IWIDTH-1:0] data_even;
    reg [3:0] 	     addr_even;
@@ -164,7 +164,7 @@ module hb_dec
      signext_data_even (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR]));
    assign 		data_even_signext[SHIFT_FACTOR-1:0] = 0;
    
-   add2_reg /* add2_and_round_reg */ #(.WIDTH(ACCWIDTH+1)) 
+   add2_reg #(.WIDTH(ACCWIDTH+1)) 
      final_adder (.clk(clk), .in1({acc_out,1'b0}), .in2({data_even_signext,1'b0}), .sum(final_sum_unrounded));
 
    wire [OWIDTH-1:0] 	bypass_data;
@@ -181,7 +181,10 @@ module hb_dec
 		 .out(bypass_data), .strobe_out(stb_bypass));
 
    // Output
-   assign stb_out = bypass ? stb_bypass : stb_final;
-   assign data_out = bypass ? bypass_data : final_sum;
+   always @(posedge clk)
+     begin
+	stb_out  <= bypass ? stb_bypass : stb_final;
+	data_out <= bypass ? bypass_data : final_sum;
+     end
    
 endmodule // hb_dec
diff --git a/usrp2/sdr_lib/hb_dec_tb.v b/usrp2/sdr_lib/hb_dec_tb.v
index 256f6085d..ac64f22a7 100644
--- a/usrp2/sdr_lib/hb_dec_tb.v
+++ b/usrp2/sdr_lib/hb_dec_tb.v
@@ -28,7 +28,7 @@ module hb_dec_tb( ) ;
     reg                     strobe_in ;
     reg     signed  [17:0]  data_in ;
     wire                    strobe_out ;
-    wire    signed  [17:0]  data_out ;
+    wire    signed  [15:0]  data_out ;
 
    initial
      begin
@@ -65,8 +65,8 @@ module hb_dec_tb( ) ;
     */
 
    
-   hb_dec #(.IWIDTH(18),.OWIDTH(18),.CWIDTH(18),.ACCWIDTH(24)) uut
-     (.clk(clock),.rst(reset),.bypass(0),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in),
+   hb_dec #(.IWIDTH(18),.OWIDTH(16),.CWIDTH(18),.ACCWIDTH(24)) uut
+     (.clk(clock),.rst(reset),.bypass(0),.run(1),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in),
       .stb_out(strobe_out),.data_out(data_out) );
    
     integer i, ri, ro, infile, outfile ;
diff --git a/usrp2/sdr_lib/input.dat b/usrp2/sdr_lib/input.dat
index 1e649ac2e..486c0252f 100644
--- a/usrp2/sdr_lib/input.dat
+++ b/usrp2/sdr_lib/input.dat
@@ -6,172 +6,6 @@
 0
 0
 0
--131072
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-131071
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-131071
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
 0
 0
 0
@@ -206,122 +40,6 @@
 0
 0
 0
--131072
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
--131072
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
-0
 0
 0
 0
@@ -339,3 +57,4 @@
 0
 0
 0
+
-- 
cgit v1.2.3


From 36e3085dfa95fa9717097541703f194d80f255f0 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Sun, 15 May 2011 14:45:32 -0700
Subject: dsp: fix off-by-one error in timing of hb_dec

---
 usrp2/sdr_lib/hb_dec.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/hb_dec.v b/usrp2/sdr_lib/hb_dec.v
index eba79b938..f4e09091f 100644
--- a/usrp2/sdr_lib/hb_dec.v
+++ b/usrp2/sdr_lib/hb_dec.v
@@ -172,7 +172,7 @@ module hb_dec
    
    round_sd #(.WIDTH_IN(ACCWIDTH-4),.WIDTH_OUT(OWIDTH))
    final_round (.clk(clk),.reset(rst),
-		.in(final_sum_unrounded[ACCWIDTH-5:0]),.strobe_in(stb_out_pre[9]),
+		.in(final_sum_unrounded[ACCWIDTH-5:0]),.strobe_in(stb_out_pre[8]),
 		.out(final_sum), .strobe_out(stb_final));
 
    round_sd #(.WIDTH_IN(IWIDTH),.WIDTH_OUT(OWIDTH))
-- 
cgit v1.2.3


From 6592deb4b1763c9b1c144a120ce86e8b07d16529 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 16 May 2011 12:03:04 -0700
Subject: dsp: add guard bit to top of cordic to allow clipping on output
 instead of wrapping

---
 usrp2/sdr_lib/dsp_core_rx.v | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 19215c777..ac8fbc6eb 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -35,7 +35,8 @@ module dsp_core_rx
    reg [31:0]  phase;
 
    wire [35:0] prod_i, prod_q;
-   wire [23:0] i_cordic, q_cordic;
+   wire [24:0] i_cordic, q_cordic;
+   wire [23:0] i_cordic_clip, q_cordic_clip;
    wire [23:0] i_cic, q_cic;
    wire [17:0] i_cic_scaled, q_cic_scaled;
    wire [17:0] i_hb1, q_hb1;
@@ -85,23 +86,26 @@ module dsp_core_rx
      else
        phase <= phase + phase_inc;
 
-   cordic_z24 #(.bitwidth(24))
+   cordic_z24 #(.bitwidth(25))
      cordic(.clock(clk), .reset(rst), .enable(run),
-	    .xi({adc_i_mux,6'd0}),. yi({adc_q_mux,6'd0}), .zi(phase[31:8]),
+	    .xi({adc_i_mux[17],adc_i_mux,6'd0}),. yi({adc_q_mux[17],adc_q_mux,6'd0}), .zi(phase[31:8]),
 	    .xo(i_cordic),.yo(q_cordic),.zo() );
 
+   clip_reg #(.bits_in(25), .bits_out(24)) clip_i (.clk(clk), .in(i_cordic), .out(i_cordic_clip));
+   clip_reg #(.bits_in(25), .bits_out(24)) clip_q (.clk(clk), .in(q_cordic), .out(q_cordic_clip));
+   
    cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
 			   .strobe_fast(1),.strobe_slow(strobe_cic) );
 
    cic_decim #(.bw(24))
      decim_i (.clock(clk),.reset(rst),.enable(run),
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
-	      .signal_in(i_cordic),.signal_out(i_cic));
+	      .signal_in(i_cordic_clip),.signal_out(i_cic));
    
    cic_decim #(.bw(24))
      decim_q (.clock(clk),.reset(rst),.enable(run),
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
-	      .signal_in(q_cordic),.signal_out(q_cic));
+	      .signal_in(q_cordic_clip),.signal_out(q_cic));
 
    wire        strobe_cic_d1;
    round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic
-- 
cgit v1.2.3


From b88383ad6289d7056e4dc50ffc892fdd0bd115e1 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 16 May 2011 18:13:58 -0700
Subject: dsp: clip in hb_dec to prevent the rare overflow with certain
 frequencies at max amplitude

---
 usrp2/sdr_lib/dsp_core_rx_tb.v | 14 ++++++++++++--
 usrp2/sdr_lib/hb_dec.v         | 11 +++++++----
 2 files changed, 19 insertions(+), 6 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx_tb.v b/usrp2/sdr_lib/dsp_core_rx_tb.v
index 67a558d55..0f36f1462 100644
--- a/usrp2/sdr_lib/dsp_core_rx_tb.v
+++ b/usrp2/sdr_lib/dsp_core_rx_tb.v
@@ -36,7 +36,7 @@ module dsp_core_rx_tb();
      (.clk(clk),.rst(rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_i(adc_in), .adc_ovf_i(0),
-      .adc_q(0), .adc_ovf_q(0),
+      .adc_q(adc_in), .adc_ovf_q(0),
       .sample({adc_out_i,adc_out_q}),
       .run(run), .strobe(), .debug());
 
@@ -53,16 +53,26 @@ module dsp_core_rx_tb();
 	set_data <= {16'd0,8'd3,8'd1}; // set decim
 	set_stb <= 1;
 	@(posedge clk);
+	set_addr <= 0;
+	//set_data <= {32'h000F_7FF9};
+	set_data <= {32'h01CA_C083}; // 700 kHz
+	set_stb <= 1;
+	@(posedge clk);
 	set_stb <= 0;
 	@(posedge clk);
 	run <= 1;
      end
+
+   always @(posedge clk)
+     //adc_in <= 18'h1FFFF;
+     adc_in <= 18'h20000;
    
+   /*
    always @(posedge clk)
      if(rst)
        adc_in <= 0;
      else
        adc_in <= adc_in + 4;
    //adc_in <= (($random % 473) + 23)/4;
-   
+*/   
 endmodule // dsp_core_rx_tb
diff --git a/usrp2/sdr_lib/hb_dec.v b/usrp2/sdr_lib/hb_dec.v
index f4e09091f..562e85b6b 100644
--- a/usrp2/sdr_lib/hb_dec.v
+++ b/usrp2/sdr_lib/hb_dec.v
@@ -95,7 +95,8 @@ module hb_dec
    // Data
    wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d;
    wire [IWIDTH-1:0] sum1, sum2;	
-   wire [OWIDTH-1:0] final_sum;
+   wire [OWIDTH:0]   final_sum;
+   wire [OWIDTH-1:0] final_sum_clip;
    reg [CWIDTH-1:0]  coeff1, coeff2;
    wire [35:0] 	     prod1, prod2;
 
@@ -170,11 +171,13 @@ module hb_dec
    wire [OWIDTH-1:0] 	bypass_data;
    wire 		stb_final, stb_bypass;
    
-   round_sd #(.WIDTH_IN(ACCWIDTH-4),.WIDTH_OUT(OWIDTH))
+   round_sd #(.WIDTH_IN(ACCWIDTH-3),.WIDTH_OUT(OWIDTH+1))
    final_round (.clk(clk),.reset(rst),
-		.in(final_sum_unrounded[ACCWIDTH-5:0]),.strobe_in(stb_out_pre[8]),
+		.in(final_sum_unrounded[ACCWIDTH-4:0]),.strobe_in(stb_out_pre[8]),
 		.out(final_sum), .strobe_out(stb_final));
 
+   clip #(.bits_in(OWIDTH+1), .bits_out(OWIDTH)) clip (.in(final_sum), .out(final_sum_clip));
+   
    round_sd #(.WIDTH_IN(IWIDTH),.WIDTH_OUT(OWIDTH))
    bypass_round (.clk(clk),.reset(rst),
 		 .in(data_in),.strobe_in(stb_in),
@@ -184,7 +187,7 @@ module hb_dec
    always @(posedge clk)
      begin
 	stb_out  <= bypass ? stb_bypass : stb_final;
-	data_out <= bypass ? bypass_data : final_sum;
+	data_out <= bypass ? bypass_data : final_sum_clip;
      end
    
 endmodule // hb_dec
-- 
cgit v1.2.3


From 6c28203a6a8c559bae81a09be41fa5a2e06a7188 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 19 May 2011 18:54:52 -0700
Subject: dsp: pass 24 bit wide signals between frontend and dsp core.
 Overkill, but we have the bits already, so why throw them away?

---
 usrp2/sdr_lib/dsp_core_rx.v | 12 ++++++------
 usrp2/sdr_lib/rx_frontend.v |  8 ++++++--
 2 files changed, 12 insertions(+), 8 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index ac8fbc6eb..e5cb95fd9 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -21,8 +21,8 @@ module dsp_core_rx
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
-   input [17:0] adc_i, input adc_ovf_i,
-   input [17:0] adc_q, input adc_ovf_q,
+   input [23:0] adc_i, input adc_ovf_i,
+   input [23:0] adc_q, input adc_ovf_q,
    
    output [31:0] sample,
    input run,
@@ -46,7 +46,7 @@ module dsp_core_rx
    wire        enable_hb1, enable_hb2;
    wire [7:0]  cic_decim_rate;
 
-   reg [17:0]  adc_i_mux, adc_q_mux;
+   reg [23:0]  adc_i_mux, adc_q_mux;
    wire        realmode;
    wire        swap_iq;
    
@@ -70,12 +70,12 @@ module dsp_core_rx
      if(swap_iq)
        begin
 	  adc_i_mux <= adc_q;
-	  adc_q_mux <= realmode ? 18'd0 : adc_i;
+	  adc_q_mux <= realmode ? 24'd0 : adc_i;
        end
      else
        begin
 	  adc_i_mux <= adc_i;
-	  adc_q_mux <= realmode ? 18'd0 : adc_q;
+	  adc_q_mux <= realmode ? 24'd0 : adc_q;
        end
    
    always @(posedge clk)
@@ -88,7 +88,7 @@ module dsp_core_rx
 
    cordic_z24 #(.bitwidth(25))
      cordic(.clock(clk), .reset(rst), .enable(run),
-	    .xi({adc_i_mux[17],adc_i_mux,6'd0}),. yi({adc_q_mux[17],adc_q_mux,6'd0}), .zi(phase[31:8]),
+	    .xi({adc_i_mux[23],adc_i_mux}),. yi({adc_q_mux[23],adc_q_mux}), .zi(phase[31:8]),
 	    .xo(i_cordic),.yo(q_cordic),.zo() );
 
    clip_reg #(.bits_in(25), .bits_out(24)) clip_i (.clk(clk), .in(i_cordic), .out(i_cordic_clip));
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index a95110240..04b14787e 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -7,7 +7,7 @@ module rx_frontend
     input [15:0] adc_a, input adc_ovf_a,
     input [15:0] adc_b, input adc_ovf_b,
 
-    output [17:0] i_out, output [17:0] q_out,
+    output [23:0] i_out, output [23:0] q_out,
     input run,
     output [31:0] debug
     );
@@ -60,10 +60,14 @@ module rx_frontend
       .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1),
       .sum(q_final), .strobe_out());
 
+   assign i_out = i_final;
+   assign q_out = q_final;
+   
+   /*
    round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i
      (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out());
    
    round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q
      (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out());
-   
+   */
 endmodule // rx_frontend
-- 
cgit v1.2.3


From f335b169f791977a2ff17f155f7e0d28c30073fb Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 24 May 2011 23:32:10 -0700
Subject: dsp: do everything at 24 bits wide

---
 usrp2/sdr_lib/dsp_core_rx.v    |  72 ++++++++++---------------
 usrp2/sdr_lib/dsp_core_rx_tb.v |  15 ++----
 usrp2/sdr_lib/hb_dec.v         | 116 ++++++++++++++++++++---------------------
 usrp2/sdr_lib/hb_dec_tb.v      |   8 +--
 usrp2/sdr_lib/input.dat        | 113 ++++++++++++++++++++++++++++++++++++++-
 5 files changed, 204 insertions(+), 120 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index e5cb95fd9..639744de7 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -30,18 +30,15 @@ module dsp_core_rx
    output [31:0] debug
    );
 
-   wire [15:0] scale_i, scale_q;
    wire [31:0] phase_inc;
    reg [31:0]  phase;
 
-   wire [35:0] prod_i, prod_q;
    wire [24:0] i_cordic, q_cordic;
    wire [23:0] i_cordic_clip, q_cordic_clip;
    wire [23:0] i_cic, q_cic;
-   wire [17:0] i_cic_scaled, q_cic_scaled;
-   wire [17:0] i_hb1, q_hb1;
-   wire [15:0] i_hb2, q_hb2;
-
+   wire [23:0] i_hb1, q_hb1;
+   wire [23:0] i_hb2, q_hb2;
+   
    wire        strobe_cic, strobe_hb1, strobe_hb2;
    wire        enable_hb1, enable_hb2;
    wire [7:0]  cic_decim_rate;
@@ -54,9 +51,11 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
    
+   /*
    setting_reg #(.my_addr(BASE+1)) sr_1
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({scale_i,scale_q}),.changed());
+   */
    
    setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -66,6 +65,8 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({realmode,swap_iq}),.changed());
 
+   // MUX so we can do realmode signals on either input
+   
    always @(posedge clk)
      if(swap_iq)
        begin
@@ -77,7 +78,8 @@ module dsp_core_rx
 	  adc_i_mux <= adc_i;
 	  adc_q_mux <= realmode ? 24'd0 : adc_q;
        end
-   
+
+   // NCO
    always @(posedge clk)
      if(rst)
        phase <= 0;
@@ -86,6 +88,7 @@ module dsp_core_rx
      else
        phase <= phase + phase_inc;
 
+   // CORDIC  24-bit I/O
    cordic_z24 #(.bitwidth(25))
      cordic(.clock(clk), .reset(rst), .enable(run),
 	    .xi({adc_i_mux[23],adc_i_mux}),. yi({adc_q_mux[23],adc_q_mux}), .zi(phase[31:8]),
@@ -93,7 +96,8 @@ module dsp_core_rx
 
    clip_reg #(.bits_in(25), .bits_out(24)) clip_i (.clk(clk), .in(i_cordic), .out(i_cordic_clip));
    clip_reg #(.bits_in(25), .bits_out(24)) clip_q (.clk(clk), .in(q_cordic), .out(q_cordic_clip));
-   
+
+   // CIC decimator  24 bit I/O
    cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
 			   .strobe_fast(1),.strobe_slow(strobe_cic) );
 
@@ -107,54 +111,32 @@ module dsp_core_rx
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
 	      .signal_in(q_cordic_clip),.signal_out(q_cic));
 
-   wire        strobe_cic_d1;
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic
-     (.clk(clk),.reset(rst), .in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1));
-   
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic
-     (.clk(clk),.reset(rst), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out());
-   
-   small_hb_dec #(.WIDTH(18)) small_hb_i
+   // First (small) halfband  24 bit I/O
+   small_hb_dec #(.WIDTH(24)) small_hb_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
-      .stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1));
+      .stb_in(strobe_cic),.data_in(i_cic),.stb_out(strobe_hb1),.data_out(i_hb1));
    
-   small_hb_dec #(.WIDTH(18)) small_hb_q
+   small_hb_dec #(.WIDTH(24)) small_hb_q
      (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
-      .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1));
+      .stb_in(strobe_cic),.data_in(q_cic),.stb_out(),.data_out(q_hb1));
 
+   // Second (large) halfband  24 bit I/O
    wire [8:0]  cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
-   hb_dec #(.IWIDTH(18), .OWIDTH(16), .CWIDTH(18), .ACCWIDTH(24)) hb_i
+   hb_dec #(.WIDTH(24)) hb_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
 
-   hb_dec #(.IWIDTH(18), .OWIDTH(16), .CWIDTH(18), .ACCWIDTH(24)) hb_q
+   hb_dec #(.WIDTH(24)) hb_q
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
-   assign      sample = {i_hb2,q_hb2};
-   assign      strobe = strobe_hb2;
+   // Round final answer to 16 bits
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i
+     (.clk(clk),.reset(rst), .in(i_hb2),.strobe_in(strobe_hb2), .out(sample[31:16]), .strobe_out(strobe));
+
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q
+     (.clk(clk),.reset(rst), .in(q_hb2),.strobe_in(strobe_hb2), .out(sample[15:0]), .strobe_out());
    
-   assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
+   assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_hb1, strobe_hb2};
    
 endmodule // dsp_core_rx
-
-/*
-   MULT18X18S mult_i
-     (.P(prod_i),    // 36-bit multiplier output
-      .A(adc_i_mux),    // 18-bit multiplier input
-      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
-      .C(clk),    // Clock input
-      .CE(1),  // Clock enable input
-      .R(rst)     // Synchronous reset input
-      );
-
-   MULT18X18S mult_q
-     (.P(prod_q),    // 36-bit multiplier output
-      .A(adc_q_mux),    // 18-bit multiplier input
-      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
-      .C(clk),    // Clock input
-      .CE(1),  // Clock enable input
-      .R(rst)     // Synchronous reset input
-      ); 
-   
-*/
diff --git a/usrp2/sdr_lib/dsp_core_rx_tb.v b/usrp2/sdr_lib/dsp_core_rx_tb.v
index 0f36f1462..c3d9882bc 100644
--- a/usrp2/sdr_lib/dsp_core_rx_tb.v
+++ b/usrp2/sdr_lib/dsp_core_rx_tb.v
@@ -12,19 +12,14 @@ module dsp_core_rx_tb();
    initial $dumpfile("dsp_core_rx_tb.vcd");
    initial $dumpvars(0,dsp_core_rx_tb);
    
-   reg [17:0] adc_in;
-   wire [15:0] adc_out_i, adc_out_q;
+   reg signed [23:0] adc_in;
+   wire signed [15:0] adc_out_i, adc_out_q;
 
    always @(posedge clk)
      begin
-	if(adc_in[17])
-	  $write("-%d,",-adc_in);
-	else
-	  $write("%d,",adc_in);
-	if(adc_out_i[15])
-	  $write("-%d\n",-adc_out_i);
-	else
-	  $write("%d\n",adc_out_i);
+	$display(adc_in);
+	$display(adc_out_i);
+	$display(adc_out_q);
      end	
 
    reg run;
diff --git a/usrp2/sdr_lib/hb_dec.v b/usrp2/sdr_lib/hb_dec.v
index 562e85b6b..8d21c21c0 100644
--- a/usrp2/sdr_lib/hb_dec.v
+++ b/usrp2/sdr_lib/hb_dec.v
@@ -22,17 +22,27 @@
 // myfilt = round(2^18 * halfgen4(.7/4,8))
 
 module hb_dec
-  #(parameter IWIDTH=18, OWIDTH=18, CWIDTH=18, ACCWIDTH=24)
+  #(parameter WIDTH=24)
     (input clk,
      input rst,
      input bypass,
      input run,
      input [8:0] cpi,  // Clocks per input -- equal to the decimation ratio ahead of this block
      input stb_in,
-     input [IWIDTH-1:0] data_in,
+     input [WIDTH-1:0] data_in,
      output reg stb_out,
-     output reg [OWIDTH-1:0] data_out);
+     output reg [WIDTH-1:0] data_out);
 
+   localparam INTWIDTH = 17;
+   localparam ACCWIDTH = WIDTH + 3;
+   
+   // Round off inputs to 17 bits because of 18 bit multipliers
+   wire [INTWIDTH-1:0] 	     data_rnd;
+   wire 		     stb_rnd;
+   
+   round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in
+     (.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd));
+   
    // Control
    reg [3:0] 		addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d;
    wire 		write_odd, write_even, do_mult;
@@ -45,16 +55,16 @@ module hb_dec
    always @(posedge clk)
      if(rst | ~run)
        odd <= 0;
-     else if(stb_in)
+     else if(stb_rnd)
        odd <= ~odd;
 
-   assign 		write_odd = stb_in & odd;
-   assign 		write_even = stb_in & ~odd;
+   assign 		write_odd = stb_rnd & odd;
+   assign 		write_even = stb_rnd & ~odd;
 
    always @(posedge clk)
      if(rst | ~run)
        phase <= 0;
-     else if(stb_in & odd)
+     else if(stb_rnd & odd)
        phase <= 1;
      else if(phase == 4)
        phase <= 0;
@@ -69,7 +79,7 @@ module hb_dec
      if(rst)
        stb_out_pre <= 0;
      else
-       stb_out_pre <= {stb_out_pre[14:0],(stb_in & odd)};
+       stb_out_pre <= {stb_out_pre[14:0],(stb_rnd & odd)};
 
    always @*
      case(phase)
@@ -93,12 +103,12 @@ module hb_dec
    assign clear = stb_out_pre[3];
    
    // Data
-   wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d;
-   wire [IWIDTH-1:0] sum1, sum2;	
-   wire [OWIDTH:0]   final_sum;
-   wire [OWIDTH-1:0] final_sum_clip;
-   reg [CWIDTH-1:0]  coeff1, coeff2;
-   wire [35:0] 	     prod1, prod2;
+   wire [INTWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d;
+   reg [INTWIDTH:0]    sum1, sum2;    // these are 18-bit inputs to mult
+   reg [WIDTH:0]       final_sum;
+   wire [WIDTH-1:0]    final_sum_clip;
+   reg [17:0] 	       coeff1, coeff2;
+   wire [35:0] 	       prod1, prod2;
 
    always @*            // Outer coeffs
      case(phase_d1)
@@ -118,19 +128,19 @@ module hb_dec
        default : coeff2 = -6107;
      endcase // case(phase)
    
-   srl #(.WIDTH(IWIDTH)) srl_odd_a
-     (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_a),.out(data_odd_a));
-   srl #(.WIDTH(IWIDTH)) srl_odd_b
-     (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_b),.out(data_odd_b));
-   srl #(.WIDTH(IWIDTH)) srl_odd_c
-     (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_c),.out(data_odd_c));
-   srl #(.WIDTH(IWIDTH)) srl_odd_d
-     (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_d),.out(data_odd_d));
-
-   add2_reg #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1));
-   add2_reg #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2));
-
-   wire [IWIDTH-1:0] data_even;
+   srl #(.WIDTH(INTWIDTH)) srl_odd_a
+     (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_a),.out(data_odd_a));
+   srl #(.WIDTH(INTWIDTH)) srl_odd_b
+     (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_b),.out(data_odd_b));
+   srl #(.WIDTH(INTWIDTH)) srl_odd_c
+     (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_c),.out(data_odd_c));
+   srl #(.WIDTH(INTWIDTH)) srl_odd_d
+     (.clk(clk),.write(write_odd),.in(data_rnd),.addr(addr_odd_d),.out(data_odd_d));
+
+   always @(posedge clk) sum1 <= {data_odd_a[INTWIDTH-1],data_odd_a} + {data_odd_b[INTWIDTH-1],data_odd_b};
+   always @(posedge clk) sum2 <= {data_odd_c[INTWIDTH-1],data_odd_c} + {data_odd_d[INTWIDTH-1],data_odd_d};
+   
+   wire [INTWIDTH-1:0] data_even;
    reg [3:0] 	     addr_even;
 
    always @(posedge clk)
@@ -141,53 +151,39 @@ module hb_dec
        default : addr_even <= 7;
      endcase // case(cpi)
    
-   srl #(.WIDTH(IWIDTH)) srl_even
-     (.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even));
-
-   localparam 		MWIDTH = ACCWIDTH-2;   
-   wire [MWIDTH-1:0] 	sum_of_prod;
+   srl #(.WIDTH(INTWIDTH)) srl_even
+     (.clk(clk),.write(write_even),.in(data_rnd),.addr(addr_even),.out(data_even));
 
    MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) );
    MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) );
-   add2_and_round_reg #(.WIDTH(MWIDTH)) 
-     add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod));
 
-   wire [ACCWIDTH-1:0] 	acc_out;
+   reg [35:0] 	     sum_of_prod;
+   always @(posedge clk) sum_of_prod <= prod1 + prod2;   // Can't overflow
    
-   acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) 
-     acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out));
+   wire [ACCWIDTH-1:0] 	acc_out;
+   acc #(.IWIDTH(ACCWIDTH-2),.OWIDTH(ACCWIDTH))
+     acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod[35:38-ACCWIDTH]),.out(acc_out));
 
-   localparam 		SHIFT_FACTOR = ACCWIDTH-IWIDTH-5;
    wire [ACCWIDTH-1:0] 	data_even_signext;
-   wire [ACCWIDTH:0] 	final_sum_unrounded;
 
-   sign_extend #(.bits_in(IWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR))
-     signext_data_even (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR]));
-   assign 		data_even_signext[SHIFT_FACTOR-1:0] = 0;
+   localparam SHIFT_FACTOR = 6;
    
-   add2_reg #(.WIDTH(ACCWIDTH+1)) 
-     final_adder (.clk(clk), .in1({acc_out,1'b0}), .in2({data_even_signext,1'b0}), .sum(final_sum_unrounded));
+   sign_extend #(.bits_in(INTWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR)) signext_data_even 
+     (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR]));
+   assign 		data_even_signext[SHIFT_FACTOR-1:0] = 0;
 
-   wire [OWIDTH-1:0] 	bypass_data;
-   wire 		stb_final, stb_bypass;
+   always @(posedge clk) final_sum <= acc_out + data_even_signext;
    
-   round_sd #(.WIDTH_IN(ACCWIDTH-3),.WIDTH_OUT(OWIDTH+1))
-   final_round (.clk(clk),.reset(rst),
-		.in(final_sum_unrounded[ACCWIDTH-4:0]),.strobe_in(stb_out_pre[8]),
-		.out(final_sum), .strobe_out(stb_final));
-
-   clip #(.bits_in(OWIDTH+1), .bits_out(OWIDTH)) clip (.in(final_sum), .out(final_sum_clip));
+   clip #(.bits_in(WIDTH+1), .bits_out(WIDTH)) clip (.in(final_sum), .out(final_sum_clip));
+   
+   // Output MUX to allow for bypass
+   wire 		selected_stb = bypass ? stb_in : stb_out_pre[8];
    
-   round_sd #(.WIDTH_IN(IWIDTH),.WIDTH_OUT(OWIDTH))
-   bypass_round (.clk(clk),.reset(rst),
-		 .in(data_in),.strobe_in(stb_in),
-		 .out(bypass_data), .strobe_out(stb_bypass));
-
-   // Output
    always @(posedge clk)
      begin
-	stb_out  <= bypass ? stb_bypass : stb_final;
-	data_out <= bypass ? bypass_data : final_sum_clip;
+	stb_out  <= selected_stb;
+	if(selected_stb)
+	  data_out <= bypass ? data_in : final_sum_clip;
      end
    
 endmodule // hb_dec
diff --git a/usrp2/sdr_lib/hb_dec_tb.v b/usrp2/sdr_lib/hb_dec_tb.v
index ac64f22a7..153cfba76 100644
--- a/usrp2/sdr_lib/hb_dec_tb.v
+++ b/usrp2/sdr_lib/hb_dec_tb.v
@@ -18,7 +18,7 @@
 module hb_dec_tb( ) ;
    
     // Parameters for instantiation
-    parameter               clocks  = 9'd2 ; // Number of clocks per input
+    parameter               clocks  = 9'd12 ; // Number of clocks per input
     parameter               decim   = 1 ; // Sets the filter to decimate
     parameter               rate    = 2 ; // Sets the decimation rate
 
@@ -26,9 +26,9 @@ module hb_dec_tb( ) ;
     reg                     reset ;
     reg                     enable ;
     reg                     strobe_in ;
-    reg     signed  [17:0]  data_in ;
+    reg     signed  [23:0]  data_in ;
     wire                    strobe_out ;
-    wire    signed  [15:0]  data_out ;
+    wire    signed  [23:0]  data_out ;
 
    initial
      begin
@@ -65,7 +65,7 @@ module hb_dec_tb( ) ;
     */
 
    
-   hb_dec #(.IWIDTH(18),.OWIDTH(16),.CWIDTH(18),.ACCWIDTH(24)) uut
+   hb_dec #(.WIDTH(24)) uut
      (.clk(clock),.rst(reset),.bypass(0),.run(1),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in),
       .stb_out(strobe_out),.data_out(data_out) );
    
diff --git a/usrp2/sdr_lib/input.dat b/usrp2/sdr_lib/input.dat
index 486c0252f..85b5887e8 100644
--- a/usrp2/sdr_lib/input.dat
+++ b/usrp2/sdr_lib/input.dat
@@ -15,7 +15,7 @@
 0
 0
 0
-100000
+8388607
 0
 0
 0
@@ -54,6 +54,117 @@
 0
 0
 0
+8388607
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+8388607
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
+0
 0
 0
 0
-- 
cgit v1.2.3


From 8217bfcafbba769677ccf299c35fd4112dcb07a7 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Wed, 25 May 2011 00:19:15 -0700
Subject: dsp: small_hb_dec now 24 bits wide as well

---
 usrp2/sdr_lib/dsp_core_rx_tb.v |  8 ++---
 usrp2/sdr_lib/small_hb_dec.v   | 69 +++++++++++++++++++++---------------------
 2 files changed, 38 insertions(+), 39 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_rx_tb.v b/usrp2/sdr_lib/dsp_core_rx_tb.v
index c3d9882bc..271db8cef 100644
--- a/usrp2/sdr_lib/dsp_core_rx_tb.v
+++ b/usrp2/sdr_lib/dsp_core_rx_tb.v
@@ -31,7 +31,7 @@ module dsp_core_rx_tb();
      (.clk(clk),.rst(rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_i(adc_in), .adc_ovf_i(0),
-      .adc_q(adc_in), .adc_ovf_q(0),
+      .adc_q(0), .adc_ovf_q(0),
       .sample({adc_out_i,adc_out_q}),
       .run(run), .strobe(), .debug());
 
@@ -49,7 +49,7 @@ module dsp_core_rx_tb();
 	set_stb <= 1;
 	@(posedge clk);
 	set_addr <= 0;
-	//set_data <= {32'h000F_7FF9};
+	//set_data <= {32'h0000_0000};
 	set_data <= {32'h01CA_C083}; // 700 kHz
 	set_stb <= 1;
 	@(posedge clk);
@@ -59,8 +59,8 @@ module dsp_core_rx_tb();
      end
 
    always @(posedge clk)
-     //adc_in <= 18'h1FFFF;
-     adc_in <= 18'h20000;
+     //adc_in <= 24'd1000000;
+     adc_in <= 24'h80_0000;
    
    /*
    always @(posedge clk)
diff --git a/usrp2/sdr_lib/small_hb_dec.v b/usrp2/sdr_lib/small_hb_dec.v
index 41ecd3e41..a7f93e056 100644
--- a/usrp2/sdr_lib/small_hb_dec.v
+++ b/usrp2/sdr_lib/small_hb_dec.v
@@ -29,21 +29,30 @@ module small_hb_dec
      input stb_in,
      input [WIDTH-1:0] data_in,
      output reg stb_out,
-     output [WIDTH-1:0] data_out);
+     output reg [WIDTH-1:0] data_out);
 
-   reg 			stb_in_d1;
-   reg [WIDTH-1:0] 	data_in_d1;
-   always @(posedge clk) stb_in_d1 <= stb_in;
-   always @(posedge clk) data_in_d1 <= data_in;
+   // Round off inputs to 17 bits because of 18 bit multipliers
+   localparam INTWIDTH = 17;
+   wire [INTWIDTH-1:0] 	data_rnd;
+   wire 		stb_rnd;
+   
+   round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(INTWIDTH)) round_in
+     (.clk(clk),.reset(rst),.in(data_in),.strobe_in(stb_in),.out(data_rnd),.strobe_out(stb_rnd));
+   	
+   
+   reg 			stb_rnd_d1;
+   reg [INTWIDTH-1:0] 	data_rnd_d1;
+   always @(posedge clk) stb_rnd_d1 <= stb_rnd;
+   always @(posedge clk) data_rnd_d1 <= data_rnd;
    
    wire 		go;
    reg 			phase, go_d1, go_d2, go_d3, go_d4;
    always @(posedge clk)
      if(rst | ~run)
        phase <= 0;
-     else if(stb_in_d1)
+     else if(stb_rnd_d1)
        phase <= ~phase;
-   assign 		go = stb_in_d1 & phase;
+   assign 		go = stb_rnd_d1 & phase;
    always @(posedge clk) 
      if(rst | ~run)
        begin
@@ -63,11 +72,11 @@ module small_hb_dec
    wire [17:0] 		coeff_a = -10690;
    wire [17:0] 		coeff_b = 75809;
    
-   reg [WIDTH-1:0] 	d1, d2, d3, d4 , d5, d6;
+   reg [INTWIDTH-1:0] 	d1, d2, d3, d4 , d5, d6;
    always @(posedge clk)
-     if(stb_in_d1 | rst)
+     if(stb_rnd_d1 | rst)
        begin
-	  d1 <= data_in_d1;
+	  d1 <= data_rnd_d1;
 	  d2 <= d1;
 	  d3 <= d2;
 	  d4 <= d3;
@@ -76,16 +85,14 @@ module small_hb_dec
        end
 
    reg [17:0] sum_a, sum_b, middle, middle_d1;
-   wire [17:0] sum_a_unreg, sum_b_unreg;
-   add2 #(.WIDTH(18)) add2_a (.in1(data_in_d1),.in2(d6),.sum(sum_a_unreg));
-   add2 #(.WIDTH(18)) add2_b (.in1(d2),.in2(d4),.sum(sum_b_unreg));
-   
+
    always @(posedge clk)
      if(go)
        begin
-	  sum_a <= sum_a_unreg;
-	  sum_b <= sum_b_unreg;
-	  middle <= d3;
+	  sum_a <= {data_rnd_d1[INTWIDTH-1],data_rnd_d1} + {d6[INTWIDTH-1],d6};
+	  sum_b <= {d2[INTWIDTH-1],d2} + {d4[INTWIDTH-1],d4};
+	  //middle <= {d3[INTWIDTH-1],d3};
+	  middle <= {d3,1'b0};
        end
 
    always @(posedge clk)
@@ -106,30 +113,22 @@ module small_hb_dec
      else if(go_d3)
        accum <= accum + {prod};
    
-   wire [18:0] 	 accum_rnd;
-   wire [17:0] 	 accum_rnd_clip;
+   wire [WIDTH:0] 	 accum_rnd;
+   wire [WIDTH-1:0] 	 accum_rnd_clip;
    
    wire 	 stb_round;
    
-   round_sd #(.WIDTH_IN(25),.WIDTH_OUT(19)) round_acc 
-     (.clk(clk), .reset(rst), .in(accum[35:11]), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round));
+   round_sd #(.WIDTH_IN(36),.WIDTH_OUT(WIDTH+1)) round_acc 
+     (.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round));
 
-   clip #(.bits_in(19),.bits_out(18)) clip (.in(accum_rnd), .out(accum_rnd_clip));
+   clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip (.in(accum_rnd), .out(accum_rnd_clip));
    
-   reg [17:0] 	 final_sum;
+   // Output
    always @(posedge clk)
-     if(bypass)
-       final_sum <= data_in_d1;
-     else if(stb_round)
-       final_sum <= accum_rnd_clip;
+     begin
+	stb_out  <= bypass ? stb_in : stb_round;
+	data_out <= bypass ? data_in : accum_rnd_clip;
+     end
 
-   assign 	 data_out = final_sum;
 
-   always @(posedge clk)
-     if(rst)
-       stb_out <= 0;
-     else if(bypass)
-       stb_out <= stb_in_d1;
-     else
-       stb_out <= stb_round;
 endmodule // small_hb_dec
-- 
cgit v1.2.3


From d7a3b89d4f7fea444602b0f8ff52029b0efa835f Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 3 Jun 2011 16:18:48 -0700
Subject: dsp: added tx_frontend, instantiated in u2/u2p

---
 usrp2/sdr_lib/Makefile.srcs  |  4 +---
 usrp2/sdr_lib/dsp_core_tx.v  | 20 ++++------------
 usrp2/sdr_lib/tx_frontend.v  | 54 ++++++++++++++++++++++++++++++++++++++++++++
 usrp2/top/N2x0/u2plus_core.v | 12 ++++++++--
 usrp2/top/USRP2/u2_core.v    | 12 ++++++++--
 usrp2/vrt/vita_tx_chain.v    |  4 ++--
 6 files changed, 81 insertions(+), 25 deletions(-)
 create mode 100644 usrp2/sdr_lib/tx_frontend.v

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/Makefile.srcs b/usrp2/sdr_lib/Makefile.srcs
index 6dab1db5e..defbced17 100644
--- a/usrp2/sdr_lib/Makefile.srcs
+++ b/usrp2/sdr_lib/Makefile.srcs
@@ -24,18 +24,16 @@ cordic.v \
 cordic_z24.v \
 cordic_stage.v \
 dsp_core_rx.v \
-dsp_core_rx_old.v \
 dsp_core_tx.v \
 hb_dec.v \
 hb_interp.v \
 round.v \
 round_reg.v \
 round_sd.v \
-rx_control.v \
 rx_dcoffset.v \
 rx_frontend.v \
 sign_extend.v \
 small_hb_dec.v \
 small_hb_int.v \
-tx_control.v \
+tx_frontend.v \
 ))
diff --git a/usrp2/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v
index 58bd82f6e..66dcee261 100644
--- a/usrp2/sdr_lib/dsp_core_tx.v
+++ b/usrp2/sdr_lib/dsp_core_tx.v
@@ -21,8 +21,7 @@ module dsp_core_tx
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
-   output reg [15:0] dac_a,
-   output reg [15:0] dac_b,
+   output [23:0] tx_i, output [23:0] tx_q,
 
    // To tx_control
    input [31:0] sample,
@@ -148,20 +147,9 @@ module dsp_core_tx
       .CE(1),  // Clock enable input
       .R(rst)     // Synchronous reset input
       );
-   
-   always @(posedge clk)
-     case(dacmux_a)
-       0 : dac_a <= prod_i[28:13];
-       1 : dac_a <= prod_q[28:13];
-       default : dac_a <= 0;
-     endcase // case(dacmux_a)
-   
-   always @(posedge clk)
-     case(dacmux_b)
-       0 : dac_b <= prod_i[28:13];
-       1 : dac_b <= prod_q[28:13];
-       default : dac_b <= 0;
-     endcase // case(dacmux_b)
+
+   assign tx_i = prod_i[28:5];
+   assign tx_q = prod_q[28:5];
    
    assign      debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
 
diff --git a/usrp2/sdr_lib/tx_frontend.v b/usrp2/sdr_lib/tx_frontend.v
new file mode 100644
index 000000000..2817c1510
--- /dev/null
+++ b/usrp2/sdr_lib/tx_frontend.v
@@ -0,0 +1,54 @@
+
+module tx_frontend
+  #(parameter BASE=0)
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [23:0] tx_i, input [23:0] tx_q, input run,
+    output reg [15:0] dac_a, output reg [15:0] dac_b
+    );
+
+   // IQ balance --> DC offset --> rounding --> mux
+
+   wire [23:0] i_dco, q_dco, i_ofs, q_ofs;
+   wire [15:0] i_final, q_final;
+   wire [7:0]  mux_ctrl;
+   
+   setting_reg #(.my_addr(BASE+0), .width(24)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(i_dco),.changed());
+
+   setting_reg #(.my_addr(BASE+1), .width(24)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(q_dco),.changed());
+
+   setting_reg #(.my_addr(BASE+2), .width(4)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(mux_ctrl),.changed());
+
+   add2_and_clip_reg #(.WIDTH(24)) add_dco_i
+     (.clk(clk), .rst(rst), .in1(i_dco), .in2(tx_i), .strobe_in(1'b1), .sum(i_ofs), .strobe_out());
+   
+   add2_and_clip_reg #(.WIDTH(24)) add_dco_q
+     (.clk(clk), .rst(rst), .in1(q_dco), .in2(tx_q), .strobe_in(1'b1), .sum(q_ofs), .strobe_out());
+   
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i
+     (.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out());
+
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q
+     (.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out());
+
+   always @(posedge clk)
+     case(mux_ctrl[3:0])
+       0 : dac_a <= i_final;
+       1 : dac_a <= q_final;
+       default : dac_a <= 0;
+     endcase // case (mux_ctrl[3:0])
+      
+   always @(posedge clk)
+     case(mux_ctrl[7:4])
+       0 : dac_b <= i_final;
+       1 : dac_b <= q_final;
+       default : dac_b <= 0;
+     endcase // case (mux_ctrl[7:4])
+      
+endmodule // tx_frontend
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 899ee472b..6154a9926 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -687,6 +687,8 @@ module u2plus_core
 	.debug(debug_extfifo),
 	.debug2(debug_extfifo2) );
 
+   wire [23:0] 	 tx_i, tx_q;
+   
    vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
 		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
 		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
@@ -697,10 +699,16 @@ module u2plus_core
       .vita_time(vita_time),
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
-      .dac_a(dac_a),.dac_b(dac_b),
+      .tx_i(tx_i),.tx_q(tx_q),
       .underrun(underrun), .run(run_tx),
       .debug(debug_vt));
-   
+
+   tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend
+     (.clk(dsp_clk), .rst(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .tx_i(tx_i), .tx_q(tx_q), .run(1'b1),
+      .dac_a(dac_a), .dac_b(dac_b));
+         
    // ///////////////////////////////////////////////////////////////////////////////////
    // SERDES
 
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 1c75f50fc..04a3cc6c9 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -684,6 +684,8 @@ module u2_core
 	.debug(debug_extfifo),
 	.debug2(debug_extfifo2) );
 
+   wire [23:0] 	 tx_i, tx_q;
+   
    vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
 		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
 		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
@@ -694,10 +696,16 @@ module u2_core
       .vita_time(vita_time),
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
-      .dac_a(dac_a),.dac_b(dac_b),
+      .tx_i(tx_i),.tx_q(tx_q),
       .underrun(underrun), .run(run_tx),
       .debug(debug_vt));
-   
+
+   tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend
+     (.clk(dsp_clk), .rst(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .tx_i(tx_i), .tx_q(tx_q), .run(1'b1),
+      .dac_a(dac_a), .dac_b(dac_b));
+         
    // ///////////////////////////////////////////////////////////////////////////////////
    // SERDES
 
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 542968afa..ac9f08fc8 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -29,7 +29,7 @@ module vita_tx_chain
     input [63:0] vita_time,
     input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o,
     output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i,
-    output [15:0] dac_a, output [15:0] dac_b,
+    output [23:0] tx_i, output [23:0] tx_q,
     output underrun, output run,
     output [31:0] debug);
 
@@ -84,7 +84,7 @@ module vita_tx_chain
      (.clk(clk),.rst(reset),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .sample(sample_tx), .run(run), .strobe(strobe_tx),
-      .dac_a(dac_a),.dac_b(dac_b),
+      .tx_i(tx_i),.tx_q(tx_q),
       .debug(debug_tx_dsp) );
 
    wire [35:0] 		flow_data, err_data_int;
-- 
cgit v1.2.3


From 5971f8e8ff288e3b1e688f6268ef536f0875238b Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 7 Jun 2011 13:32:18 -0700
Subject: dsp: remove unused setting reg

---
 usrp2/sdr_lib/dsp_core_tx.v | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v
index 66dcee261..f02c63b42 100644
--- a/usrp2/sdr_lib/dsp_core_tx.v
+++ b/usrp2/sdr_lib/dsp_core_tx.v
@@ -49,10 +49,6 @@ module dsp_core_tx
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
 
-   setting_reg #(.my_addr(BASE+4), .width(8)) sr_4
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out({dacmux_b,dacmux_a}),.changed());
-
    // Strobes are all now delayed by 1 cycle for timing reasons
    wire        strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
    reg 	       strobe_cic = 1;
-- 
cgit v1.2.3


From 9613e9d9f4dce93a090c2b94f24135a4e06653ee Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Sun, 12 Jun 2011 21:32:38 -0700
Subject: dsp: implement iqbal on tx

---
 usrp2/sdr_lib/tx_dcoffset.v | 26 --------------------------
 usrp2/sdr_lib/tx_frontend.v | 39 +++++++++++++++++++++++++++++++++++----
 2 files changed, 35 insertions(+), 30 deletions(-)
 delete mode 100644 usrp2/sdr_lib/tx_dcoffset.v

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/tx_dcoffset.v b/usrp2/sdr_lib/tx_dcoffset.v
deleted file mode 100644
index 737693611..000000000
--- a/usrp2/sdr_lib/tx_dcoffset.v
+++ /dev/null
@@ -1,26 +0,0 @@
-
-// TX DC offset.  Setting is 8 fractional bits, 8 integer bits
-
-module tx_dcoffset 
-  #(parameter WIDTH_IN=16,
-    parameter WIDTH_OUT=16,
-    parameter ADDR=8'd0)
-   (input clk, input rst, 
-    input set_stb, input [7:0] set_addr, input [31:0] set_data,
-    input [WIDTH_IN-1:0] in, output [WIDTH_OUT-1:0] out);
-
-   wire [15:0] 		 dco;
-   wire [WIDTH_IN+8-1:0] dco_ext, sum;
- 
-   setting_reg #(.my_addr(ADDR),.width(16)) sr_0
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(dco));
-   
-   sign_extend #(.bits_in(16),.bits_out(WIDTH_IN+8)) ext_err (.in(dco), .out(dco_ext));
- 
-   add2_and_clip_reg #(.WIDTH(WIDTH_IN+8)) add2_and_clip_reg
-     (.clk(clk), .rst(rst), .in1({in,8'd0}), .in2(dco_ext), .strobe_in(1'b1), .sum(sum), .strobe_out());
-
-   round_sd #(.WIDTH_IN(WIDTH_IN+8),.WIDTH_OUT(WIDTH_OUT)) round_sd
-     (.clk(clk), .reset(rst), .in(sum), .strobe_in(1'b1), .out(out), .strobe_out());
-   
-endmodule // rx_dcoffset
diff --git a/usrp2/sdr_lib/tx_frontend.v b/usrp2/sdr_lib/tx_frontend.v
index 2817c1510..82476ad0d 100644
--- a/usrp2/sdr_lib/tx_frontend.v
+++ b/usrp2/sdr_lib/tx_frontend.v
@@ -12,6 +12,9 @@ module tx_frontend
    wire [23:0] i_dco, q_dco, i_ofs, q_ofs;
    wire [15:0] i_final, q_final;
    wire [7:0]  mux_ctrl;
+   wire [35:0] corr_i, corr_q;
+   wire [23:0] i_bal, q_bal;
+   wire [17:0] mag_corr, phase_corr;
    
    setting_reg #(.my_addr(BASE+0), .width(24)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -21,22 +24,50 @@ module tx_frontend
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(q_dco),.changed());
 
-   setting_reg #(.my_addr(BASE+2), .width(4)) sr_2
+   setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(mag_corr),.changed());
+   
+   setting_reg #(.my_addr(BASE+3),.width(18)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_corr),.changed());
+  
+   setting_reg #(.my_addr(BASE+4), .width(8)) sr_4
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(mux_ctrl),.changed());
 
+   // IQ Balance
+   MULT18X18S mult_mag_corr
+     (.P(corr_i), .A(tx_i[23:6]), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); 
+   
+   MULT18X18S mult_phase_corr
+     (.P(corr_q), .A(tx_i[23:6]), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
+   
+   add2_and_clip_reg #(.WIDTH(24)) add_clip_i
+     (.clk(clk), .rst(rst), 
+      .in1(tx_i), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), 
+      .sum(i_bal), .strobe_out());
+   
+   add2_and_clip_reg #(.WIDTH(24)) add_clip_q
+     (.clk(clk), .rst(rst), 
+      .in1(tx_q), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1),
+      .sum(q_bal), .strobe_out());
+
+   // DC Offset
    add2_and_clip_reg #(.WIDTH(24)) add_dco_i
-     (.clk(clk), .rst(rst), .in1(i_dco), .in2(tx_i), .strobe_in(1'b1), .sum(i_ofs), .strobe_out());
+     (.clk(clk), .rst(rst), .in1(i_dco), .in2(i_bal), .strobe_in(1'b1), .sum(i_ofs), .strobe_out());
    
    add2_and_clip_reg #(.WIDTH(24)) add_dco_q
-     (.clk(clk), .rst(rst), .in1(q_dco), .in2(tx_q), .strobe_in(1'b1), .sum(q_ofs), .strobe_out());
-   
+     (.clk(clk), .rst(rst), .in1(q_dco), .in2(q_bal), .strobe_in(1'b1), .sum(q_ofs), .strobe_out());
+
+   // Rounding
    round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i
      (.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out());
 
    round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q
      (.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out());
 
+   // Mux
    always @(posedge clk)
      case(mux_ctrl[3:0])
        0 : dac_a <= i_final;
-- 
cgit v1.2.3


From 948b90267866ceada3aef7960d9d7f6292e68f19 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 14 Jun 2011 20:58:51 -0700
Subject: u1e-dsp: attach tx dc offset and iq balance

---
 usrp2/sdr_lib/tx_frontend.v |  9 +++++----
 usrp2/top/E1x0/u1e_core.v   | 15 +++++++++------
 2 files changed, 14 insertions(+), 10 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/tx_frontend.v b/usrp2/sdr_lib/tx_frontend.v
index 82476ad0d..283ed451e 100644
--- a/usrp2/sdr_lib/tx_frontend.v
+++ b/usrp2/sdr_lib/tx_frontend.v
@@ -1,10 +1,11 @@
 
 module tx_frontend
-  #(parameter BASE=0)
+  #(parameter BASE=0,
+    parameter WIDTH_OUT=16)
    (input clk, input rst,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
     input [23:0] tx_i, input [23:0] tx_q, input run,
-    output reg [15:0] dac_a, output reg [15:0] dac_b
+    output reg [WIDTH_OUT-1:0] dac_a, output reg [WIDTH_OUT-1:0] dac_b
     );
 
    // IQ balance --> DC offset --> rounding --> mux
@@ -61,10 +62,10 @@ module tx_frontend
      (.clk(clk), .rst(rst), .in1(q_dco), .in2(q_bal), .strobe_in(1'b1), .sum(q_ofs), .strobe_out());
 
    // Rounding
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_i
      (.clk(clk), .reset(rst), .in(i_ofs),.strobe_in(1'b1), .out(i_final), .strobe_out());
 
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(WIDTH_OUT)) round_q
      (.clk(clk), .reset(rst), .in(q_ofs),.strobe_in(1'b1), .out(q_final), .strobe_out());
 
    // Mux
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index e038b78b8..3d5dced29 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -223,7 +223,7 @@ module u1e_core
    // ///////////////////////////////////////////////////////////////////////////////////
    // DSP TX
 
-   wire [15:0] 	 tx_i_int, tx_q_int;
+   wire [23:0] 	 tx_i_int, tx_q_int;
    wire 	 run_tx;
    
    vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
@@ -236,13 +236,16 @@ module u1e_core
       .vita_time(vita_time),
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
-      .dac_a(tx_i_int),.dac_b(tx_q_int),
+      .tx_i(tx_i_int),.tx_q(tx_q_int),
       .underrun(tx_underrun_dsp), .run(run_tx),
       .debug(debug_vt));
-   
-   assign tx_i = tx_i_int[15:2];
-   assign tx_q = tx_q_int[15:2];
-   
+
+   tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend
+     (.clk(dsp_clk), .rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1),
+      .dac_a(tx_i), .dac_b(tx_q));
+
    // /////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Intercon, single master
    wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
-- 
cgit v1.2.3


From 10d489c3aee1b09dec3171f70251c95e744c5afc Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Thu, 16 Jun 2011 11:31:27 -0700
Subject: u1p/u1e: cleanup some warnings, connect the correct clocks

---
 usrp2/sdr_lib/tx_frontend.v  |  2 +-
 usrp2/top/B100/u1plus_core.v | 15 +++++++--------
 usrp2/top/E1x0/u1e_core.v    |  6 +++---
 3 files changed, 11 insertions(+), 12 deletions(-)

(limited to 'usrp2/sdr_lib')

diff --git a/usrp2/sdr_lib/tx_frontend.v b/usrp2/sdr_lib/tx_frontend.v
index 283ed451e..d8525dd25 100644
--- a/usrp2/sdr_lib/tx_frontend.v
+++ b/usrp2/sdr_lib/tx_frontend.v
@@ -11,7 +11,7 @@ module tx_frontend
    // IQ balance --> DC offset --> rounding --> mux
 
    wire [23:0] i_dco, q_dco, i_ofs, q_ofs;
-   wire [15:0] i_final, q_final;
+   wire [WIDTH_OUT-1:0] i_final, q_final;
    wire [7:0]  mux_ctrl;
    wire [35:0] corr_i, corr_q;
    wire [23:0] i_bal, q_bal;
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index cc27a3c12..3b2667e5b 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -57,8 +57,7 @@ module u1plus_core
    localparam SR_CLEAR_TX_FIFO = 62; // 1 reg
    localparam SR_GLOBAL_RESET = 63;  // 1 reg
 
-   
-   wire [7:0]	COMPAT_NUM = 8'd4;
+   wire [7:0]	COMPAT_NUM = 8'd5;
    
    wire 	wb_clk = clk_fpga;
    wire 	wb_rst, global_reset;
@@ -79,11 +78,11 @@ module u1plus_core
    wire [31:0] 	debug_vt;
    wire 	gpif_rst;
    
-   wire 	rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc;
    reg [7:0] 	frames_per_packet;
    
-   assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp;
-   assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp;
+   wire 	rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpif, tx_underrun_dsp, tx_underrun_gpif;
+   wire 	rx_overrun = rx_overrun_gpif | rx_overrun_dsp0 | rx_overrun_dsp1;
+   wire 	tx_underrun = tx_underrun_gpif | tx_underrun_dsp;
    
    setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset
      (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
@@ -104,7 +103,7 @@ module u1plus_core
    wire [sw-1:0] m0_sel;
    wire 	 m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty;
 
-   wire [31:0] 	 debug_gpmc;
+   wire [31:0] 	 debug_gpif;
 
    wire [35:0] 	 tx_data, rx_data, tx_err_data;
    wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, 
@@ -135,7 +134,7 @@ module u1plus_core
 	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
 	 .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy),
 	 
-	 .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
+	 .tx_underrun(tx_underrun_gpif), .rx_overrun(rx_overrun_gpif),
 
 	 .frames_per_packet(frames_per_packet), .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl),
 	 .debug0(debug0), .debug1(debug1));
@@ -229,7 +228,7 @@ module u1plus_core
       .debug(debug_vt));
 
    tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend
-     (.clk(dsp_clk), .rst(dsp_rst),
+     (.clk(wb_clk), .rst(wb_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1),
       .dac_a(tx_i), .dac_b(tx_q));
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index dff712a2f..b74f51d3c 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -76,8 +76,8 @@ module u1e_core
 
    wire [31:0] 	debug_vt;
    wire 	rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc;
-   assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp0 | rx_overrun_dsp1;
-   assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp;
+   wire 	rx_overrun = rx_overrun_gpmc | rx_overrun_dsp0 | rx_overrun_dsp1;
+   wire 	tx_underrun = tx_underrun_gpmc | tx_underrun_dsp;
    
    setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset
      (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
@@ -241,7 +241,7 @@ module u1e_core
       .debug(debug_vt));
 
    tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend
-     (.clk(dsp_clk), .rst(dsp_rst),
+     (.clk(wb_clk), .rst(wb_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .tx_i(tx_i_int), .tx_q(tx_q_int), .run(1'b1),
       .dac_a(tx_i), .dac_b(tx_q));
-- 
cgit v1.2.3