From f8a04a4879260b2692b823a067a63c3ca5e35731 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 7 Mar 2011 23:09:06 -0800 Subject: u2/u2p: pull IQ balance and dcoffset out of dsp_core, put in frontend module --- usrp2/sdr_lib/rx_frontend.v | 75 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 usrp2/sdr_lib/rx_frontend.v (limited to 'usrp2/sdr_lib/rx_frontend.v') diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v new file mode 100644 index 000000000..f5271a207 --- /dev/null +++ b/usrp2/sdr_lib/rx_frontend.v @@ -0,0 +1,75 @@ + +module rx_frontend + #(parameter BASE = 0) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [15:0] adc_a, input adc_ovf_a, + input [15:0] adc_b, input adc_ovf_b, + + output [17:0] i_out, output [17:0] q_out, + input run, + output [31:0] debug + ); + + reg [15:0] adc_i, adc_q; + wire [17:0] adc_i_ofs, adc_q_ofs; + wire [35:0] corr_i, corr_q; + wire [17:0] scale_i, scale_q; + wire [7:0] muxctrl; + wire [23:0] i_final, q_final; + + setting_reg #(.my_addr(BASE), .width(8)) sr_8 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(muxctrl),.changed()); + + always @(posedge clk) + case(muxctrl[3:0]) // The I mapping + 0: adc_i <= adc_a; + 1: adc_i <= adc_b; + 2: adc_i <= 0; + default: adc_i <= 0; + endcase // case (muxctrl[3:0]) + + always @(posedge clk) + case(muxctrl[7:4]) // The Q mapping + 0: adc_q <= adc_a; + 1: adc_q <= adc_b; + 2: adc_q <= 0; + default: adc_q <= 0; + endcase // case (muxctrl[7:4]) + + setting_reg #(.my_addr(BASE+1),.width(18)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(scale_i),.changed()); + + setting_reg #(.my_addr(BASE+2),.width(18)) sr_2 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(scale_q),.changed()); + + rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .in({adc_i,2'b00}),.out(adc_i_ofs)); + + rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q + (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .in({adc_q,2'b00}),.out(adc_q_ofs)); + + MULT18X18S mult_i + (.P(corr_q), .A(adc_i_ofs), .B(scale_i), .C(clk), .CE(1), .R(rst) ); + + MULT18X18S mult_q + (.P(corr_i), .A(adc_i_ofs), .B(scale_q), .C(clk), .CE(1), .R(rst) ); + + add2_and_clip_reg #(.WIDTH(24)) add_clip_i + (.clk(clk), .rst(rst), + .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final)); + + add2_and_clip_reg #(.WIDTH(24)) add_clip_q + (.clk(clk), .rst(rst), + .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final)); + + assign i_out = i_final[23:6]; + assign q_out = q_final[23:6]; + +endmodule // rx_frontend -- cgit v1.2.3 From 2bad9b4d2711ad3aeef2e3b35153b2463874940e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 11 Mar 2011 13:43:51 -0800 Subject: u2/u2p: misc connection and compilation fixes --- usrp2/sdr_lib/Makefile.srcs | 1 + usrp2/sdr_lib/dsp_core_rx.v | 21 +++++++++++---------- usrp2/sdr_lib/rx_frontend.v | 16 ++++++++-------- usrp2/top/USRP2/u2_core.v | 4 ++-- 4 files changed, 22 insertions(+), 20 deletions(-) (limited to 'usrp2/sdr_lib/rx_frontend.v') diff --git a/usrp2/sdr_lib/Makefile.srcs b/usrp2/sdr_lib/Makefile.srcs index 90eede20f..4a85726a9 100644 --- a/usrp2/sdr_lib/Makefile.srcs +++ b/usrp2/sdr_lib/Makefile.srcs @@ -30,6 +30,7 @@ round.v \ round_reg.v \ rx_control.v \ rx_dcoffset.v \ +rx_frontend.v \ sign_extend.v \ small_hb_dec.v \ small_hb_int.v \ diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index 36d56174e..ae6cdbdf3 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -21,8 +21,8 @@ module dsp_core_rx (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [17:0] adc_i, input adc_ovf_a, - input [17:0] adc_q, input adc_ovf_b, + input [17:0] adc_i, input adc_ovf_i, + input [17:0] adc_q, input adc_ovf_q, output [31:0] sample, input run, @@ -31,7 +31,6 @@ module dsp_core_rx ); wire [15:0] scale_i, scale_q; - reg [13:0] adc_i, adc_q; wire [31:0] phase_inc; reg [31:0] phase; @@ -69,7 +68,7 @@ module dsp_core_rx MULT18X18S mult_i (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input + .A(adc_i), // 18-bit multiplier input .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input .C(clk), // Clock input .CE(1), // Clock enable input @@ -78,7 +77,7 @@ module dsp_core_rx MULT18X18S mult_q (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input + .A(adc_q), // 18-bit multiplier input .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input .C(clk), // Clock input .CE(1), // Clock enable input @@ -125,11 +124,13 @@ module dsp_core_rx (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); - round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); - round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out)); - - assign sample = sample_reg; - assign strobe = strobe_hb2; + round_reg #(.bits_in(18),.bits_out(16)) round_iout (.clk(clk),.in(i_hb2),.out(i_out)); + round_reg #(.bits_in(18),.bits_out(16)) round_qout (.clk(clk),.in(q_hb2),.out(q_out)); + reg strobe_out; + always @(posedge clk) strobe_out <= strobe_hb2; + + assign sample = {i_hb2,q_hb2}; + assign strobe = strobe_out; assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2}; endmodule // dsp_core_rx diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v index f5271a207..3b05a4a08 100644 --- a/usrp2/sdr_lib/rx_frontend.v +++ b/usrp2/sdr_lib/rx_frontend.v @@ -15,7 +15,7 @@ module rx_frontend reg [15:0] adc_i, adc_q; wire [17:0] adc_i_ofs, adc_q_ofs; wire [35:0] corr_i, corr_q; - wire [17:0] scale_i, scale_q; + wire [17:0] mag_corr,phase_corr; wire [7:0] muxctrl; wire [23:0] i_final, q_final; @@ -41,11 +41,11 @@ module rx_frontend setting_reg #(.my_addr(BASE+1),.width(18)) sr_1 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(scale_i),.changed()); + .in(set_data),.out(mag_corr),.changed()); setting_reg #(.my_addr(BASE+2),.width(18)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(scale_q),.changed()); + .in(set_data),.out(phase_corr),.changed()); rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -55,12 +55,12 @@ module rx_frontend (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .in({adc_q,2'b00}),.out(adc_q_ofs)); - MULT18X18S mult_i - (.P(corr_q), .A(adc_i_ofs), .B(scale_i), .C(clk), .CE(1), .R(rst) ); - - MULT18X18S mult_q - (.P(corr_i), .A(adc_i_ofs), .B(scale_q), .C(clk), .CE(1), .R(rst) ); + MULT18X18S mult_mag_corr + (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); + MULT18X18S mult_phase_corr + (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) ); + add2_and_clip_reg #(.WIDTH(24)) add_clip_i (.clk(clk), .rst(rst), .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final)); diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 691b60c1c..151ac27ae 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -604,7 +604,7 @@ module u2_core dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b), + .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), .debug() ); @@ -632,7 +632,7 @@ module u2_core dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b), + .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), .debug() ); -- cgit v1.2.3 From 90c74cd45885ab2aba3d090a8deebd11b96c6d7c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 18 Apr 2011 14:13:50 -0700 Subject: u2/u2p: use new rx_frontend in u2 and u2p --- usrp2/sdr_lib/rx_frontend.v | 4 ++-- usrp2/top/N2x0/u2plus_core.v | 15 +++++++++++++-- usrp2/top/USRP2/u2_core.v | 4 ++-- 3 files changed, 17 insertions(+), 6 deletions(-) (limited to 'usrp2/sdr_lib/rx_frontend.v') diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v index 3b05a4a08..0ad83f6c7 100644 --- a/usrp2/sdr_lib/rx_frontend.v +++ b/usrp2/sdr_lib/rx_frontend.v @@ -69,7 +69,7 @@ module rx_frontend (.clk(clk), .rst(rst), .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final)); - assign i_out = i_final[23:6]; - assign q_out = q_final[23:6]; + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i (.clk(clk), .reset(rst), .in(i_final), .out(i_out)); + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q (.clk(clk), .reset(rst), .in(q_final), .out(q_out)); endmodule // rx_frontend diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index 8a7c6ddee..3d67b0dcf 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -583,6 +583,17 @@ module u2plus_core .ss_pad_o(spiflash_cs), .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); + // ///////////////////////////////////////////////////////////////////////// + // ADC Frontend + wire [17:0] adc_i, adc_q; + + rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), + .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b), + .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); + // ///////////////////////////////////////////////////////////////////////// // DSP RX 0 wire [31:0] sample_rx0; @@ -594,7 +605,7 @@ module u2plus_core dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), .debug() ); @@ -622,7 +633,7 @@ module u2plus_core dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b), .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), .debug() ); diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 151ac27ae..0821277cc 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -283,7 +283,7 @@ module u2_core .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); - ////////////////////////////////////////////////////////////////////////////////////////// + // //////////////////////////////////////////////////////////////////////////////////////// // Reset Controller system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), .ram_loader_rst_o(ram_loader_rst), @@ -586,7 +586,7 @@ module u2_core // ADC Frontend wire [17:0] adc_i, adc_q; - rx_frontend #(.BASE()) rx_frontend + rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), -- cgit v1.2.3 From 568535308d377eeb459a385f7a10b40cbe73a4d9 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 9 May 2011 17:20:32 -0700 Subject: dsp: add2_and_clip_reg and round_sd now are now strobed to be compatible with strobed (non-full rate) data --- usrp2/sdr_lib/add2_and_clip_reg.v | 9 +++++++-- usrp2/sdr_lib/dsp_core_rx.v | 20 +++++++++++--------- usrp2/sdr_lib/round_sd.v | 5 +++-- usrp2/sdr_lib/round_sd_tb.v | 21 ++++++++++++++------- usrp2/sdr_lib/rx_dcoffset.v | 4 ++-- usrp2/sdr_lib/rx_frontend.v | 13 +++++++++---- 6 files changed, 46 insertions(+), 26 deletions(-) (limited to 'usrp2/sdr_lib/rx_frontend.v') diff --git a/usrp2/sdr_lib/add2_and_clip_reg.v b/usrp2/sdr_lib/add2_and_clip_reg.v index 7070f1cea..8073b3b54 100644 --- a/usrp2/sdr_lib/add2_and_clip_reg.v +++ b/usrp2/sdr_lib/add2_and_clip_reg.v @@ -5,7 +5,9 @@ module add2_and_clip_reg input rst, input [WIDTH-1:0] in1, input [WIDTH-1:0] in2, - output reg [WIDTH-1:0] sum); + input strobe_in, + output reg [WIDTH-1:0] sum, + output reg strobe_out); wire [WIDTH-1:0] sum_int; @@ -14,7 +16,10 @@ module add2_and_clip_reg always @(posedge clk) if(rst) sum <= 0; - else + else if(strobe_in) sum <= sum_int; + + always @(posedge clk) + strobe_out <= strobe_in; endmodule // add2_and_clip_reg diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index f17c2816f..6a12836f2 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -102,10 +102,12 @@ module dsp_core_rx .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic), .signal_in(q_cordic),.signal_out(q_cic)); - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled)); - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled)); - reg strobe_cic_d1; - always @(posedge clk) strobe_cic_d1 <= strobe_cic; + wire strobe_cic_d1; + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) + round_icic (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1)); + + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) + round_qcic (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out()); small_hb_dec #(.WIDTH(18)) small_hb_i (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), @@ -124,13 +126,13 @@ module dsp_core_rx (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); - round_reg #(.bits_in(18),.bits_out(16)) round_iout (.clk(clk),.in(i_hb2),.out(i_out)); - round_reg #(.bits_in(18),.bits_out(16)) round_qout (.clk(clk),.in(q_hb2),.out(q_out)); - reg strobe_out; - always @(posedge clk) strobe_out <= strobe_hb2; + round_sd #(.bits_in(18),.bits_out(16)) + round_iout (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe)); + + round_sd #(.bits_in(18),.bits_out(16)) + round_qout (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out()); assign sample = {i_hb2,q_hb2}; - assign strobe = strobe_out; assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2}; endmodule // dsp_core_rx diff --git a/usrp2/sdr_lib/round_sd.v b/usrp2/sdr_lib/round_sd.v index b77c1471b..aeeb3502f 100644 --- a/usrp2/sdr_lib/round_sd.v +++ b/usrp2/sdr_lib/round_sd.v @@ -4,7 +4,8 @@ module round_sd #(parameter WIDTH_IN=18, parameter WIDTH_OUT=16) (input clk, input reset, - input [WIDTH_IN-1:0] in, output [WIDTH_OUT-1:0] out); + input [WIDTH_IN-1:0] in, input strobe_in, + output [WIDTH_OUT-1:0] out, output strobe_out); localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1; @@ -14,7 +15,7 @@ module round_sd sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext)); add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg - (.clk(clk), .rst(reset), .in1(in), .in2(err_ext), .sum(sum)); + (.clk(clk), .rst(reset), .in1(in), .in2(err_ext), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_out)); round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err)); diff --git a/usrp2/sdr_lib/round_sd_tb.v b/usrp2/sdr_lib/round_sd_tb.v index 80b3707dc..1e8e9a323 100644 --- a/usrp2/sdr_lib/round_sd_tb.v +++ b/usrp2/sdr_lib/round_sd_tb.v @@ -11,8 +11,8 @@ module round_sd_tb(); initial $dumpfile("round_sd_tb.vcd"); initial $dumpvars(0,round_sd_tb); - localparam WIDTH_IN = 14; - localparam WIDTH_OUT = 10; + localparam WIDTH_IN = 8; + localparam WIDTH_OUT = 5; reg [WIDTH_IN-1:0] adc_in, adc_in_del; wire [WIDTH_OUT-1:0] adc_out; @@ -37,15 +37,22 @@ module round_sd_tb(); end round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT)) - round_sd(.clk(clk),.reset(rst), .in(adc_in),.out(adc_out)); + round_sd(.clk(clk),.reset(rst), .in(adc_in), .strobe_in(1'b1), .out(adc_out), .strobe_out()); + reg [5:0] counter = 0; + always @(posedge clk) - adc_in <= 14'h1FDF; - //adc_in <= $random % 4739; - + counter <= counter+1; + always @(posedge clk) adc_in_del <= adc_in; - initial #10000 $finish; + always @(posedge clk) + if(rst) + adc_in <= 0; + else if(counter == 63) + adc_in <= adc_in + 1; + + initial #300000 $finish; endmodule // longfifo_tb diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v index 97923b9bf..350579056 100644 --- a/usrp2/sdr_lib/rx_dcoffset.v +++ b/usrp2/sdr_lib/rx_dcoffset.v @@ -49,9 +49,9 @@ module rx_dcoffset integrator <= integrator + {{(alpha_shift){out[WIDTH-1]}},out}; round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd - (.clk(clk), .reset(rst), .in(integrator), .out(quantized)); + (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), strobe_out()); add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg - (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .sum(out)); + (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), strobe_out()); endmodule // rx_dcoffset diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v index 0ad83f6c7..98f72509c 100644 --- a/usrp2/sdr_lib/rx_frontend.v +++ b/usrp2/sdr_lib/rx_frontend.v @@ -63,13 +63,18 @@ module rx_frontend add2_and_clip_reg #(.WIDTH(24)) add_clip_i (.clk(clk), .rst(rst), - .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final)); + .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), + .sum(i_final), .strobe_out()); add2_and_clip_reg #(.WIDTH(24)) add_clip_q (.clk(clk), .rst(rst), - .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final)); + .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), + .sum(q_final), .strobe_out()); - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i (.clk(clk), .reset(rst), .in(i_final), .out(i_out)); - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q (.clk(clk), .reset(rst), .in(q_final), .out(q_out)); + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) + round_i (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out()); + + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) + round_q (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out()); endmodule // rx_frontend -- cgit v1.2.3 From 2e2de3f8f7e055c9f583a17a513774f307ffbc04 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 9 May 2011 17:28:54 -0700 Subject: dsp: fix typos --- usrp2/sdr_lib/dsp_core_rx.v | 16 ++++++++-------- usrp2/sdr_lib/rx_dcoffset.v | 4 ++-- usrp2/sdr_lib/rx_frontend.v | 8 ++++---- 3 files changed, 14 insertions(+), 14 deletions(-) (limited to 'usrp2/sdr_lib/rx_frontend.v') diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index 6a12836f2..8c8297124 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -103,11 +103,11 @@ module dsp_core_rx .signal_in(q_cordic),.signal_out(q_cic)); wire strobe_cic_d1; - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) - round_icic (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1)); + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic + (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1)); - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) - round_qcic (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out()); + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic + (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out()); small_hb_dec #(.WIDTH(18)) small_hb_i (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run), @@ -126,11 +126,11 @@ module dsp_core_rx (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb), .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2)); - round_sd #(.bits_in(18),.bits_out(16)) - round_iout (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe)); + round_sd #(.bits_in(18),.bits_out(16)) round_iout + (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe)); - round_sd #(.bits_in(18),.bits_out(16)) - round_qout (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out()); + round_sd #(.bits_in(18),.bits_out(16)) round_qout + (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out()); assign sample = {i_hb2,q_hb2}; assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2}; diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v index 350579056..e43461261 100644 --- a/usrp2/sdr_lib/rx_dcoffset.v +++ b/usrp2/sdr_lib/rx_dcoffset.v @@ -49,9 +49,9 @@ module rx_dcoffset integrator <= integrator + {{(alpha_shift){out[WIDTH-1]}},out}; round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd - (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), strobe_out()); + (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), .strobe_out()); add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg - (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), strobe_out()); + (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), .strobe_out()); endmodule // rx_dcoffset diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v index 98f72509c..f93172f16 100644 --- a/usrp2/sdr_lib/rx_frontend.v +++ b/usrp2/sdr_lib/rx_frontend.v @@ -71,10 +71,10 @@ module rx_frontend .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), .sum(q_final), .strobe_out()); - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) - round_i (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out()); + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i + (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out()); - round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) - round_q (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out()); + round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q + (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out()); endmodule // rx_frontend -- cgit v1.2.3 From 3993b882c9f3aa69b1cdb6e7370bedd6d9e7931a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 11 May 2011 17:57:45 -0700 Subject: dsp: reworked muxes on rx --- usrp2/sdr_lib/dsp_core_rx.v | 24 ++++++++++++++++++++++-- usrp2/sdr_lib/rx_frontend.v | 29 +++++++++-------------------- 2 files changed, 31 insertions(+), 22 deletions(-) (limited to 'usrp2/sdr_lib/rx_frontend.v') diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index afba3428e..1b04c4f36 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -46,6 +46,10 @@ module dsp_core_rx wire enable_hb1, enable_hb2; wire [7:0] cic_decim_rate; + reg [17:0] adc_i_mux, adc_q_mux; + wire realmode; + wire swap_iq; + setting_reg #(.my_addr(BASE+0)) sr_0 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phase_inc),.changed()); @@ -58,6 +62,22 @@ module dsp_core_rx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed()); + setting_reg #(.my_addr(BASE+3), .width(2)) sr_3 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({realmode,swap_iq}),.changed()); + + always @(posedge clk) + if(swap_iq) + begin + adc_i_mux <= adc_q; + adc_q_mux <= realmode ? 18'd0 : adc_i; + end + else + begin + adc_i_mux <= adc_i; + adc_q_mux <= realmode ? 18'd0 : adc_q; + end + always @(posedge clk) if(rst) phase <= 0; @@ -68,7 +88,7 @@ module dsp_core_rx MULT18X18S mult_i (.P(prod_i), // 36-bit multiplier output - .A(adc_i), // 18-bit multiplier input + .A(adc_i_mux), // 18-bit multiplier input .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input .C(clk), // Clock input .CE(1), // Clock enable input @@ -77,7 +97,7 @@ module dsp_core_rx MULT18X18S mult_q (.P(prod_q), // 36-bit multiplier output - .A(adc_q), // 18-bit multiplier input + .A(adc_q_mux), // 18-bit multiplier input .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input .C(clk), // Clock input .CE(1), // Clock enable input diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v index f93172f16..a95110240 100644 --- a/usrp2/sdr_lib/rx_frontend.v +++ b/usrp2/sdr_lib/rx_frontend.v @@ -14,31 +14,20 @@ module rx_frontend reg [15:0] adc_i, adc_q; wire [17:0] adc_i_ofs, adc_q_ofs; - wire [35:0] corr_i, corr_q; - wire [17:0] mag_corr,phase_corr; - wire [7:0] muxctrl; + wire [35:0] corr_i, corr_q; wire [17:0] mag_corr,phase_corr; + wire swap_iq; wire [23:0] i_final, q_final; - setting_reg #(.my_addr(BASE), .width(8)) sr_8 + setting_reg #(.my_addr(BASE), .width(1)) sr_8 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); + .in(set_data),.out(swap_iq),.changed()); always @(posedge clk) - case(muxctrl[3:0]) // The I mapping - 0: adc_i <= adc_a; - 1: adc_i <= adc_b; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case (muxctrl[3:0]) - - always @(posedge clk) - case(muxctrl[7:4]) // The Q mapping - 0: adc_q <= adc_a; - 1: adc_q <= adc_b; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case (muxctrl[7:4]) - + if(swap_iq) // Swap + {adc_i,adc_q} <= {adc_b,adc_a}; + else + {adc_i,adc_q} <= {adc_a,adc_b}; + setting_reg #(.my_addr(BASE+1),.width(18)) sr_1 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(mag_corr),.changed()); -- cgit v1.2.3 From 6c28203a6a8c559bae81a09be41fa5a2e06a7188 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 19 May 2011 18:54:52 -0700 Subject: dsp: pass 24 bit wide signals between frontend and dsp core. Overkill, but we have the bits already, so why throw them away? --- usrp2/sdr_lib/dsp_core_rx.v | 12 ++++++------ usrp2/sdr_lib/rx_frontend.v | 8 ++++++-- 2 files changed, 12 insertions(+), 8 deletions(-) (limited to 'usrp2/sdr_lib/rx_frontend.v') diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index ac8fbc6eb..e5cb95fd9 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -21,8 +21,8 @@ module dsp_core_rx (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, - input [17:0] adc_i, input adc_ovf_i, - input [17:0] adc_q, input adc_ovf_q, + input [23:0] adc_i, input adc_ovf_i, + input [23:0] adc_q, input adc_ovf_q, output [31:0] sample, input run, @@ -46,7 +46,7 @@ module dsp_core_rx wire enable_hb1, enable_hb2; wire [7:0] cic_decim_rate; - reg [17:0] adc_i_mux, adc_q_mux; + reg [23:0] adc_i_mux, adc_q_mux; wire realmode; wire swap_iq; @@ -70,12 +70,12 @@ module dsp_core_rx if(swap_iq) begin adc_i_mux <= adc_q; - adc_q_mux <= realmode ? 18'd0 : adc_i; + adc_q_mux <= realmode ? 24'd0 : adc_i; end else begin adc_i_mux <= adc_i; - adc_q_mux <= realmode ? 18'd0 : adc_q; + adc_q_mux <= realmode ? 24'd0 : adc_q; end always @(posedge clk) @@ -88,7 +88,7 @@ module dsp_core_rx cordic_z24 #(.bitwidth(25)) cordic(.clock(clk), .reset(rst), .enable(run), - .xi({adc_i_mux[17],adc_i_mux,6'd0}),. yi({adc_q_mux[17],adc_q_mux,6'd0}), .zi(phase[31:8]), + .xi({adc_i_mux[23],adc_i_mux}),. yi({adc_q_mux[23],adc_q_mux}), .zi(phase[31:8]), .xo(i_cordic),.yo(q_cordic),.zo() ); clip_reg #(.bits_in(25), .bits_out(24)) clip_i (.clk(clk), .in(i_cordic), .out(i_cordic_clip)); diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v index a95110240..04b14787e 100644 --- a/usrp2/sdr_lib/rx_frontend.v +++ b/usrp2/sdr_lib/rx_frontend.v @@ -7,7 +7,7 @@ module rx_frontend input [15:0] adc_a, input adc_ovf_a, input [15:0] adc_b, input adc_ovf_b, - output [17:0] i_out, output [17:0] q_out, + output [23:0] i_out, output [23:0] q_out, input run, output [31:0] debug ); @@ -60,10 +60,14 @@ module rx_frontend .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1), .sum(q_final), .strobe_out()); + assign i_out = i_final; + assign q_out = q_final; + + /* round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out()); round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out()); - + */ endmodule // rx_frontend -- cgit v1.2.3