From ce43cdfc6782b9f24781170f8f78a96e93bb2365 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Sun, 5 Dec 2010 20:33:05 -0800
Subject: redone DC offset with sigma-delta quantization

---
 usrp2/sdr_lib/rx_dcoffset.v | 51 ++++++++++++++++++++++++++-------------------
 1 file changed, 29 insertions(+), 22 deletions(-)

(limited to 'usrp2/sdr_lib/rx_dcoffset.v')

diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 64ff4110d..35dfb07ae 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -18,43 +18,50 @@
 
 
 module rx_dcoffset 
-  #(parameter WIDTH=14,
-    parameter ADDR=8'd0)
-    (input clk, input rst, 
-     input set_stb, input [7:0] set_addr, input [31:0] set_data,
-     input signed [WIDTH-1:0] adc_in, output signed [WIDTH-1:0] adc_out);
-
-   // Because of some extra delays to make timing easier, the transfer function is:
-   //     (z-1)/(z^2-z-alpha)  where alpha is 1/2^n
+  #(parameter WIDTH=16,
+    parameter ADDR=8'd0,
+    parameter alpha_shift=16)
+   (input clk, input rst, 
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [WIDTH-1:0] in, output [WIDTH-1:0] out);
    
-   wire 	       set_now = set_stb & (ADDR == set_addr);
+   wire 	      set_now = set_stb & (ADDR == set_addr);
    
-   reg 		       fixed;  // uses fixed offset
-   wire 	       signed [WIDTH-1:0] fixed_dco;
-   reg 		       signed [31:0] integrator;
+   reg 		      fixed;  // uses fixed offset
+   wire [WIDTH-1:0]   fixed_dco;
 
+   localparam int_width = WIDTH + alpha_shift;
+   reg [int_width-1:0] integrator;
+   
    always @(posedge clk)
      if(rst)
        begin
 	  fixed <= 0;
-	  integrator <= 32'd0;
+	  integrator <= {int_width{1'b0}};
        end
      else if(set_now)
        begin
-	  integrator <= {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}};
+	  //integrator <= {set_data[30:0],{(31-int_width){1'b0}}};
 	  fixed <= set_data[31];
        end
      else if(~fixed)
-       integrator <= integrator + adc_out;
-   
-   wire [WIDTH:0] scaled_integrator;
+       integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
+
+   wire [WIDTH-1:0] quantized;
+   wire [int_width-WIDTH:0] q_err;
+   wire [int_width-1:0]     q_err_ext;
+   wire [int_width-1:0]     q_loop;
+
+   round #(.bits_in(int_width), .bits_out(WIDTH)) quantizer
+     (.in(q_loop), .out(quantized), .err(q_err));
    
-   round #(.bits_in(33),.bits_out(15)) round (.in({integrator[31],integrator}),.out(scaled_integrator));
+   sign_extend #(.bits_in(int_width-WIDTH+1),.bits_out(int_width)) sign_extend
+     (.in(q_err), .out(q_err_ext));
    
-   wire [WIDTH:0]      adc_out_int = {adc_in[WIDTH-1],adc_in} - scaled_integrator;
-
-   clip_reg #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip_adc
-     (.clk(clk),.in(adc_out_int),.out(adc_out));
+   add2_and_clip_reg #(.WIDTH(int_width)) sd_fixed
+     (.clk(clk), .rst(rst), .in1(integrator), .in2(q_err_ext), .sum(q_loop));
    
+   add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
+     (.clk(clk), .in1(in), .in2(-quantized), .sum(out));
 
 endmodule // rx_dcoffset
-- 
cgit v1.2.3


From f8a04a4879260b2692b823a067a63c3ca5e35731 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 7 Mar 2011 23:09:06 -0800
Subject: u2/u2p:  pull IQ balance and dcoffset out of dsp_core, put in
 frontend module

---
 usrp2/sdr_lib/dsp_core_rx.v | 43 ++------------------------
 usrp2/sdr_lib/rx_dcoffset.v |  2 +-
 usrp2/sdr_lib/rx_frontend.v | 75 +++++++++++++++++++++++++++++++++++++++++++++
 usrp2/top/USRP2/u2_core.v   | 15 +++++++--
 4 files changed, 91 insertions(+), 44 deletions(-)
 create mode 100644 usrp2/sdr_lib/rx_frontend.v

(limited to 'usrp2/sdr_lib/rx_dcoffset.v')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 0e69e53f7..9aee52131 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -21,8 +21,8 @@ module dsp_core_rx
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
-   input [13:0] adc_a, input adc_ovf_a,
-   input [13:0] adc_b, input adc_ovf_b,
+   input [17:0] adc_i, input adc_ovf_a,
+   input [17:0] adc_q, input adc_ovf_b,
    
    output [31:0] sample,
    input run,
@@ -60,40 +60,6 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
 
-   rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a
-     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .adc_in(adc_a),.adc_out(adc_a_ofs));
-   
-   rx_dcoffset #(.WIDTH(14),.ADDR(BASE+4)) rx_dcoffset_b
-     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .adc_in(adc_b),.adc_out(adc_b_ofs));
-
-   wire [7:0]  muxctrl;
-   setting_reg #(.my_addr(BASE+5), .width(8)) sr_8
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(muxctrl),.changed());
-
-   wire [1:0] gpio_ena;
-   setting_reg #(.my_addr(BASE+6), .width(2)) sr_9
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(gpio_ena),.changed());
-
-   always @(posedge clk)
-     case(muxctrl[3:0])		// The I mapping
-       0: adc_i <= adc_a_ofs;
-       1: adc_i <= adc_b_ofs;
-       2: adc_i <= 0;
-       default: adc_i <= 0;
-     endcase // case (muxctrl[3:0])
-   
-   always @(posedge clk)
-     case(muxctrl[7:4])		// The Q mapping
-       0: adc_q <= adc_a_ofs;
-       1: adc_q <= adc_b_ofs;
-       2: adc_q <= 0;
-       default: adc_q <= 0;
-     endcase // case (muxctrl[7:4])
-          
    always @(posedge clk)
      if(rst)
        phase <= 0;
@@ -119,7 +85,6 @@ module dsp_core_rx
       .CE(1),  // Clock enable input
       .R(rst)     // Synchronous reset input
       ); 
-
    
    cordic_z24 #(.bitwidth(24))
      cordic(.clock(clk), .reset(rst), .enable(run),
@@ -164,10 +129,6 @@ module dsp_core_rx
    round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out));
    round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out));
 
-   reg [31:0] sample_reg;
-   always @(posedge clk)
-     sample_reg <= {i_out,q_out};
-   
    assign      sample = sample_reg;
    assign      strobe = strobe_hb2;
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 35dfb07ae..52f8cd5be 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -62,6 +62,6 @@ module rx_dcoffset
      (.clk(clk), .rst(rst), .in1(integrator), .in2(q_err_ext), .sum(q_loop));
    
    add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
-     (.clk(clk), .in1(in), .in2(-quantized), .sum(out));
+     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .sum(out));
 
 endmodule // rx_dcoffset
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
new file mode 100644
index 000000000..f5271a207
--- /dev/null
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -0,0 +1,75 @@
+
+module rx_frontend
+  #(parameter BASE = 0)
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    input [15:0] adc_a, input adc_ovf_a,
+    input [15:0] adc_b, input adc_ovf_b,
+
+    output [17:0] i_out, output [17:0] q_out,
+    input run,
+    output [31:0] debug
+    );
+   
+   reg [15:0] 	  adc_i, adc_q;
+   wire [17:0] 	  adc_i_ofs, adc_q_ofs;
+   wire [35:0] 	  corr_i, corr_q;
+   wire [17:0] 	  scale_i, scale_q;
+   wire [7:0] 	  muxctrl;
+   wire [23:0] 	  i_final, q_final;
+   
+   setting_reg #(.my_addr(BASE), .width(8)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(muxctrl),.changed());
+
+   always @(posedge clk)
+     case(muxctrl[3:0])		// The I mapping
+       0: adc_i <= adc_a;
+       1: adc_i <= adc_b;
+       2: adc_i <= 0;
+       default: adc_i <= 0;
+     endcase // case (muxctrl[3:0])
+   
+   always @(posedge clk)
+     case(muxctrl[7:4])		// The Q mapping
+       0: adc_q <= adc_a;
+       1: adc_q <= adc_b;
+       2: adc_q <= 0;
+       default: adc_q <= 0;
+     endcase // case (muxctrl[7:4])
+   
+   setting_reg #(.my_addr(BASE+1),.width(18)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(scale_i),.changed());
+   
+   setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(scale_q),.changed());
+   
+   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .in({adc_i,2'b00}),.out(adc_i_ofs));
+   
+   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .in({adc_q,2'b00}),.out(adc_q_ofs));
+   
+   MULT18X18S mult_i
+     (.P(corr_q), .A(adc_i_ofs), .B(scale_i), .C(clk), .CE(1), .R(rst) );
+   
+   MULT18X18S mult_q
+     (.P(corr_i), .A(adc_i_ofs), .B(scale_q), .C(clk), .CE(1), .R(rst) ); 
+
+   add2_and_clip_reg #(.WIDTH(24)) add_clip_i
+     (.clk(clk), .rst(rst), 
+      .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final));
+   
+   add2_and_clip_reg #(.WIDTH(24)) add_clip_q
+     (.clk(clk), .rst(rst), 
+      .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final));
+
+   assign i_out = i_final[23:6];
+   assign q_out = q_final[23:6];
+   
+endmodule // rx_frontend
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index ca9762ac5..691b60c1c 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -582,6 +582,17 @@ module u2_core
 
    assign sd_dat_i[31:8] = 0;
 
+   // /////////////////////////////////////////////////////////////////////////
+   // ADC Frontend
+   wire [17:0] 	 adc_i, adc_q;
+   
+   rx_frontend #(.BASE()) rx_frontend
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a),
+      .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b),
+      .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug());
+   
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 0
    wire [31:0] 	 sample_rx0;
@@ -593,7 +604,7 @@ module u2_core
    dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b),
       .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
       .debug() );
 
@@ -621,7 +632,7 @@ module u2_core
    dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .adc_a(adc_i),.adc_ovf_a(adc_ovf_a),.adc_b(adc_q),.adc_ovf_b(adc_ovf_b),
       .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
       .debug() );
 
-- 
cgit v1.2.3


From 7b127e2f51f636baf1d39f46cc9afd09579bf74f Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 18 Apr 2011 13:59:43 -0700
Subject: dsp: use sigma delta rounding in rx_dcoffset and in dsp_core_rx

---
 usrp2/sdr_lib/dsp_core_rx.v |  4 ++--
 usrp2/sdr_lib/rx_dcoffset.v | 18 ++++--------------
 2 files changed, 6 insertions(+), 16 deletions(-)

(limited to 'usrp2/sdr_lib/rx_dcoffset.v')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index ae6cdbdf3..f17c2816f 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -102,8 +102,8 @@ module dsp_core_rx
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
 	      .signal_in(q_cordic),.signal_out(q_cic));
 
-   round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
-   round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
    reg 	       strobe_cic_d1;
    always @(posedge clk) strobe_cic_d1 <= strobe_cic;
    
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 52f8cd5be..97923b9bf 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -32,7 +32,8 @@ module rx_dcoffset
 
    localparam int_width = WIDTH + alpha_shift;
    reg [int_width-1:0] integrator;
-   
+   wire [WIDTH-1:0]    quantized;
+
    always @(posedge clk)
      if(rst)
        begin
@@ -47,19 +48,8 @@ module rx_dcoffset
      else if(~fixed)
        integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
 
-   wire [WIDTH-1:0] quantized;
-   wire [int_width-WIDTH:0] q_err;
-   wire [int_width-1:0]     q_err_ext;
-   wire [int_width-1:0]     q_loop;
-
-   round #(.bits_in(int_width), .bits_out(WIDTH)) quantizer
-     (.in(q_loop), .out(quantized), .err(q_err));
-   
-   sign_extend #(.bits_in(int_width-WIDTH+1),.bits_out(int_width)) sign_extend
-     (.in(q_err), .out(q_err_ext));
-   
-   add2_and_clip_reg #(.WIDTH(int_width)) sd_fixed
-     (.clk(clk), .rst(rst), .in1(integrator), .in2(q_err_ext), .sum(q_loop));
+   round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
+     (.clk(clk), .reset(rst), .in(integrator), .out(quantized));
    
    add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
      (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .sum(out));
-- 
cgit v1.2.3


From 568535308d377eeb459a385f7a10b40cbe73a4d9 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 9 May 2011 17:20:32 -0700
Subject: dsp: add2_and_clip_reg and round_sd now are now strobed to be
 compatible with strobed (non-full rate) data

---
 usrp2/sdr_lib/add2_and_clip_reg.v |  9 +++++++--
 usrp2/sdr_lib/dsp_core_rx.v       | 20 +++++++++++---------
 usrp2/sdr_lib/round_sd.v          |  5 +++--
 usrp2/sdr_lib/round_sd_tb.v       | 21 ++++++++++++++-------
 usrp2/sdr_lib/rx_dcoffset.v       |  4 ++--
 usrp2/sdr_lib/rx_frontend.v       | 13 +++++++++----
 6 files changed, 46 insertions(+), 26 deletions(-)

(limited to 'usrp2/sdr_lib/rx_dcoffset.v')

diff --git a/usrp2/sdr_lib/add2_and_clip_reg.v b/usrp2/sdr_lib/add2_and_clip_reg.v
index 7070f1cea..8073b3b54 100644
--- a/usrp2/sdr_lib/add2_and_clip_reg.v
+++ b/usrp2/sdr_lib/add2_and_clip_reg.v
@@ -5,7 +5,9 @@ module add2_and_clip_reg
      input rst,
      input [WIDTH-1:0] in1,
      input [WIDTH-1:0] in2,
-     output reg [WIDTH-1:0] sum);
+     input strobe_in,
+     output reg [WIDTH-1:0] sum,
+     output reg strobe_out);
 
    wire [WIDTH-1:0] sum_int;
    
@@ -14,7 +16,10 @@ module add2_and_clip_reg
    always @(posedge clk)
      if(rst)
        sum <= 0;
-     else
+     else if(strobe_in)
        sum <= sum_int;
+
+   always @(posedge clk)
+     strobe_out <= strobe_in;
    
 endmodule // add2_and_clip_reg
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index f17c2816f..6a12836f2 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -102,10 +102,12 @@ module dsp_core_rx
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
 	      .signal_in(q_cordic),.signal_out(q_cic));
 
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
-   reg 	       strobe_cic_d1;
-   always @(posedge clk) strobe_cic_d1 <= strobe_cic;
+   wire        strobe_cic_d1;
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_icic (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1));
+   
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_qcic (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out());
    
    small_hb_dec #(.WIDTH(18)) small_hb_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
@@ -124,13 +126,13 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
-   round_reg #(.bits_in(18),.bits_out(16)) round_iout (.clk(clk),.in(i_hb2),.out(i_out));
-   round_reg #(.bits_in(18),.bits_out(16)) round_qout (.clk(clk),.in(q_hb2),.out(q_out));
-   reg 	       strobe_out;
-   always @(posedge clk) strobe_out <= strobe_hb2;
+   round_sd #(.bits_in(18),.bits_out(16)) 
+   round_iout (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
+   
+   round_sd #(.bits_in(18),.bits_out(16)) 
+   round_qout (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
    
    assign      sample = {i_hb2,q_hb2};
-   assign      strobe = strobe_out;
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
    
 endmodule // dsp_core_rx
diff --git a/usrp2/sdr_lib/round_sd.v b/usrp2/sdr_lib/round_sd.v
index b77c1471b..aeeb3502f 100644
--- a/usrp2/sdr_lib/round_sd.v
+++ b/usrp2/sdr_lib/round_sd.v
@@ -4,7 +4,8 @@ module round_sd
   #(parameter WIDTH_IN=18,
     parameter WIDTH_OUT=16)
    (input clk, input reset,
-    input [WIDTH_IN-1:0] in, output [WIDTH_OUT-1:0] out);
+    input [WIDTH_IN-1:0] in, input strobe_in,
+    output [WIDTH_OUT-1:0] out, output strobe_out);
 
    localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1;
 
@@ -14,7 +15,7 @@ module round_sd
    sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext));
    
    add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg
-     (.clk(clk), .rst(reset), .in1(in), .in2(err_ext), .sum(sum));
+     (.clk(clk), .rst(reset), .in1(in), .in2(err_ext), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_out));
    
    round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err));
    
diff --git a/usrp2/sdr_lib/round_sd_tb.v b/usrp2/sdr_lib/round_sd_tb.v
index 80b3707dc..1e8e9a323 100644
--- a/usrp2/sdr_lib/round_sd_tb.v
+++ b/usrp2/sdr_lib/round_sd_tb.v
@@ -11,8 +11,8 @@ module round_sd_tb();
    initial $dumpfile("round_sd_tb.vcd");
    initial $dumpvars(0,round_sd_tb);
 
-   localparam WIDTH_IN = 14;
-   localparam WIDTH_OUT = 10;
+   localparam WIDTH_IN = 8;
+   localparam WIDTH_OUT = 5;
    
    reg [WIDTH_IN-1:0] adc_in, adc_in_del;
    wire [WIDTH_OUT-1:0] adc_out;
@@ -37,15 +37,22 @@ module round_sd_tb();
 	end	
    
    round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT)) 
-   round_sd(.clk(clk),.reset(rst), .in(adc_in),.out(adc_out));
+   round_sd(.clk(clk),.reset(rst), .in(adc_in), .strobe_in(1'b1), .out(adc_out), .strobe_out());
 
+   reg [5:0] counter = 0;
+   
    always @(posedge clk)
-     adc_in <= 14'h1FDF;
-     //adc_in <= $random % 4739;
-
+     counter <= counter+1;
+   
    always @(posedge clk)
      adc_in_del <= adc_in;
 
-   initial #10000 $finish;
+   always @(posedge clk)
+     if(rst)
+       adc_in <= 0;
+     else if(counter == 63)
+       adc_in <= adc_in + 1;
+   
+   initial #300000 $finish;
    
 endmodule // longfifo_tb
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 97923b9bf..350579056 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -49,9 +49,9 @@ module rx_dcoffset
        integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
 
    round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
-     (.clk(clk), .reset(rst), .in(integrator), .out(quantized));
+     (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), strobe_out());
    
    add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
-     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .sum(out));
+     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), strobe_out());
 
 endmodule // rx_dcoffset
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index 0ad83f6c7..98f72509c 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -63,13 +63,18 @@ module rx_frontend
    
    add2_and_clip_reg #(.WIDTH(24)) add_clip_i
      (.clk(clk), .rst(rst), 
-      .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final));
+      .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), 
+      .sum(i_final), .strobe_out());
    
    add2_and_clip_reg #(.WIDTH(24)) add_clip_q
      (.clk(clk), .rst(rst), 
-      .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final));
+      .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1),
+      .sum(q_final), .strobe_out());
 
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i (.clk(clk), .reset(rst), .in(i_final), .out(i_out));
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q (.clk(clk), .reset(rst), .in(q_final), .out(q_out));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_i (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out());
+   
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_q (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out());
    
 endmodule // rx_frontend
-- 
cgit v1.2.3


From 2e2de3f8f7e055c9f583a17a513774f307ffbc04 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 9 May 2011 17:28:54 -0700
Subject: dsp: fix typos

---
 usrp2/sdr_lib/dsp_core_rx.v | 16 ++++++++--------
 usrp2/sdr_lib/rx_dcoffset.v |  4 ++--
 usrp2/sdr_lib/rx_frontend.v |  8 ++++----
 3 files changed, 14 insertions(+), 14 deletions(-)

(limited to 'usrp2/sdr_lib/rx_dcoffset.v')

diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 6a12836f2..8c8297124 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -103,11 +103,11 @@ module dsp_core_rx
 	      .signal_in(q_cordic),.signal_out(q_cic));
 
    wire        strobe_cic_d1;
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
-   round_icic (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic
+     (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1));
    
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
-   round_qcic (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out());
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic
+     (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out());
    
    small_hb_dec #(.WIDTH(18)) small_hb_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
@@ -126,11 +126,11 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
-   round_sd #(.bits_in(18),.bits_out(16)) 
-   round_iout (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
+   round_sd #(.bits_in(18),.bits_out(16)) round_iout
+     (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
    
-   round_sd #(.bits_in(18),.bits_out(16)) 
-   round_qout (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
+   round_sd #(.bits_in(18),.bits_out(16)) round_qout
+     (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
    
    assign      sample = {i_hb2,q_hb2};
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 350579056..e43461261 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -49,9 +49,9 @@ module rx_dcoffset
        integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
 
    round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
-     (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), strobe_out());
+     (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), .strobe_out());
    
    add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
-     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), strobe_out());
+     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), .strobe_out());
 
 endmodule // rx_dcoffset
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index 98f72509c..f93172f16 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -71,10 +71,10 @@ module rx_frontend
       .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1),
       .sum(q_final), .strobe_out());
 
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
-   round_i (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out());
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i
+     (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out());
    
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
-   round_q (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out());
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q
+     (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out());
    
 endmodule // rx_frontend
-- 
cgit v1.2.3