From e633f884d728c24e6f5749d5821b9c62ec8fd17e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 27 Jan 2012 11:52:19 -0800 Subject: dsp rework: renamed dsp signals for frontend IO --- usrp2/sdr_lib/duc_chain.v | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'usrp2/sdr_lib/duc_chain.v') diff --git a/usrp2/sdr_lib/duc_chain.v b/usrp2/sdr_lib/duc_chain.v index 248870a69..f1c32a1b2 100644 --- a/usrp2/sdr_lib/duc_chain.v +++ b/usrp2/sdr_lib/duc_chain.v @@ -1,5 +1,5 @@ // -// Copyright 2011 Ettus Research LLC +// Copyright 2011-2012 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -18,14 +18,15 @@ //! The USRP digital up-conversion chain module duc_chain - #(parameter BASE=0) + #(parameter BASE = 0, parameter DSPNO = 0) (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, - output [23:0] dac_i, - output [23:0] dac_q, + // From TX frontend + output [23:0] tx_fe_i, + output [23:0] tx_fe_q, - // To tx_control + // To TX control input [31:0] sample, input run, output strobe, @@ -36,7 +37,7 @@ module duc_chain wire [31:0] phase_inc; reg [31:0] phase; wire [7:0] interp_rate; - wire [3:0] dacmux_a, dacmux_b; + wire [3:0] tx_femux_a, tx_femux_b; wire enable_hb1, enable_hb2; wire rate_change; @@ -147,8 +148,8 @@ module duc_chain .R(rst) // Synchronous reset input ); - assign tx_i = prod_i[28:5]; - assign tx_q = prod_q[28:5]; + assign tx_fe_i = prod_i[28:5]; + assign tx_fe_q = prod_q[28:5]; assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run}; -- cgit v1.2.3