From 7bf8a6df381a667134b55701993c6770d32bc76b Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Fri, 22 Jan 2010 11:56:55 -0800
Subject: Moved usrp2 fpga files into usrp2 subdir.

---
 usrp2/sdr_lib/clip_reg.v | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 usrp2/sdr_lib/clip_reg.v

(limited to 'usrp2/sdr_lib/clip_reg.v')

diff --git a/usrp2/sdr_lib/clip_reg.v b/usrp2/sdr_lib/clip_reg.v
new file mode 100644
index 000000000..d5e98d982
--- /dev/null
+++ b/usrp2/sdr_lib/clip_reg.v
@@ -0,0 +1,38 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input clk,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out);
+   
+   wire [bits_out-1:0] temp;
+
+   clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp));
+   always @(posedge clk)
+     out <= temp;
+   
+endmodule // clip_reg
+
-- 
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