From f64f1b5c86c605b7c769bbedd565e356d08e925d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 10 Nov 2010 17:24:29 -0800 Subject: reverting part of the reversion of the spi settings. --- usrp2/opencores/spi/rtl/verilog/spi_defines.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'usrp2/opencores/spi/rtl') diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v index 86c301886..3e4dd0e3c 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -43,8 +43,8 @@ // low frequency of system clock this can be reduced. // Use SPI_DIVIDER_LEN for fine tuning theexact number. // -//`define SPI_DIVIDER_LEN_8 -`define SPI_DIVIDER_LEN_16 +`define SPI_DIVIDER_LEN_8 +//`define SPI_DIVIDER_LEN_16 //`define SPI_DIVIDER_LEN_24 //`define SPI_DIVIDER_LEN_32 -- cgit v1.2.3