From ba97786f44d66c634f289e9a23021e8e13548326 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 22 Feb 2010 12:33:13 -0800
Subject: remove the #1 delay in all the regs. They just slow down sims.
---
usrp2/opencores/spi/rtl/verilog/spi_clgen.v | 20 +++---
usrp2/opencores/spi/rtl/verilog/spi_defines.v | 8 +--
usrp2/opencores/spi/rtl/verilog/spi_shift.v | 90 +++++++++++++--------------
usrp2/opencores/spi/rtl/verilog/spi_top.v | 68 ++++++++++----------
4 files changed, 90 insertions(+), 96 deletions(-)
(limited to 'usrp2/opencores/spi/rtl')
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
index 7bc4f6e5e..3f29f6d7f 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
@@ -43,8 +43,6 @@
module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge);
- parameter Tp = 1;
-
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
@@ -71,13 +69,13 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
always @(posedge clk_in or posedge rst)
begin
if(rst)
- cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}};
+ cnt <= {`SPI_DIVIDER_LEN{1'b1}};
else
begin
if(!enable || cnt_zero)
- cnt <= #Tp divider;
+ cnt <= divider;
else
- cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
+ cnt <= cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
end
end
@@ -85,9 +83,9 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
always @(posedge clk_in or posedge rst)
begin
if(rst)
- clk_out <= #Tp 1'b0;
+ clk_out <= 1'b0;
else
- clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
+ clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
@@ -95,13 +93,13 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
begin
if(rst)
begin
- pos_edge <= #Tp 1'b0;
- neg_edge <= #Tp 1'b0;
+ pos_edge <= 1'b0;
+ neg_edge <= 1'b0;
end
else
begin
- pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
- neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
+ pos_edge <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
+ neg_edge <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index a6925918e..01de2584d 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -43,8 +43,8 @@
// low frequency of system clock this can be reduced.
// Use SPI_DIVIDER_LEN for fine tuning theexact number.
//
-//`define SPI_DIVIDER_LEN_8
-`define SPI_DIVIDER_LEN_16
+`define SPI_DIVIDER_LEN_8
+//`define SPI_DIVIDER_LEN_16
//`define SPI_DIVIDER_LEN_24
//`define SPI_DIVIDER_LEN_32
@@ -66,9 +66,9 @@
// Use SPI_MAX_CHAR for fine tuning the exact number, when using
// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
//
-`define SPI_MAX_CHAR_128
+//`define SPI_MAX_CHAR_128
//`define SPI_MAX_CHAR_64
-//`define SPI_MAX_CHAR_32
+`define SPI_MAX_CHAR_32
//`define SPI_MAX_CHAR_24
//`define SPI_MAX_CHAR_16
//`define SPI_MAX_CHAR_8
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/opencores/spi/rtl/verilog/spi_shift.v
index b17ac8b1f..c8c73706b 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_shift.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_shift.v
@@ -46,8 +46,6 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
tip, last,
p_in, p_out, s_clk, s_in, s_out);
- parameter Tp = 1;
-
input clk; // system clock
input rst; // reset
input [3:0] latch; // latch signal for storing the data in shift register
@@ -92,13 +90,13 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
always @(posedge clk or posedge rst)
begin
if(rst)
- cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
+ cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}};
else
begin
if(tip)
- cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
+ cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else
- cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
+ cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
@@ -106,132 +104,132 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
always @(posedge clk or posedge rst)
begin
if(rst)
- tip <= #Tp 1'b0;
+ tip <= 1'b0;
else if(go && ~tip)
- tip <= #Tp 1'b1;
+ tip <= 1'b1;
else if(tip && last && pos_edge)
- tip <= #Tp 1'b0;
+ tip <= 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
- s_out <= #Tp 1'b0;
+ s_out <= 1'b0;
else
- s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
+ s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
// Receiving bits from the line
always @(posedge clk or posedge rst)
begin
if (rst)
- data <= #Tp {`SPI_MAX_CHAR{1'b0}};
+ data <= {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
else if (latch[0] && !tip)
begin
if (byte_sel[3])
- data[31:24] <= #Tp p_in[31:24];
+ data[31:24] <= p_in[31:24];
if (byte_sel[2])
- data[23:16] <= #Tp p_in[23:16];
+ data[23:16] <= p_in[23:16];
if (byte_sel[1])
- data[15:8] <= #Tp p_in[15:8];
+ data[15:8] <= p_in[15:8];
if (byte_sel[0])
- data[7:0] <= #Tp p_in[7:0];
+ data[7:0] <= p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
- data[63:56] <= #Tp p_in[31:24];
+ data[63:56] <= p_in[31:24];
if (byte_sel[2])
- data[55:48] <= #Tp p_in[23:16];
+ data[55:48] <= p_in[23:16];
if (byte_sel[1])
- data[47:40] <= #Tp p_in[15:8];
+ data[47:40] <= p_in[15:8];
if (byte_sel[0])
- data[39:32] <= #Tp p_in[7:0];
+ data[39:32] <= p_in[7:0];
end
else if (latch[2] && !tip)
begin
if (byte_sel[3])
- data[95:88] <= #Tp p_in[31:24];
+ data[95:88] <= p_in[31:24];
if (byte_sel[2])
- data[87:80] <= #Tp p_in[23:16];
+ data[87:80] <= p_in[23:16];
if (byte_sel[1])
- data[79:72] <= #Tp p_in[15:8];
+ data[79:72] <= p_in[15:8];
if (byte_sel[0])
- data[71:64] <= #Tp p_in[7:0];
+ data[71:64] <= p_in[7:0];
end
else if (latch[3] && !tip)
begin
if (byte_sel[3])
- data[127:120] <= #Tp p_in[31:24];
+ data[127:120] <= p_in[31:24];
if (byte_sel[2])
- data[119:112] <= #Tp p_in[23:16];
+ data[119:112] <= p_in[23:16];
if (byte_sel[1])
- data[111:104] <= #Tp p_in[15:8];
+ data[111:104] <= p_in[15:8];
if (byte_sel[0])
- data[103:96] <= #Tp p_in[7:0];
+ data[103:96] <= p_in[7:0];
end
`else
`ifdef SPI_MAX_CHAR_64
else if (latch[0] && !tip)
begin
if (byte_sel[3])
- data[31:24] <= #Tp p_in[31:24];
+ data[31:24] <= p_in[31:24];
if (byte_sel[2])
- data[23:16] <= #Tp p_in[23:16];
+ data[23:16] <= p_in[23:16];
if (byte_sel[1])
- data[15:8] <= #Tp p_in[15:8];
+ data[15:8] <= p_in[15:8];
if (byte_sel[0])
- data[7:0] <= #Tp p_in[7:0];
+ data[7:0] <= p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
- data[63:56] <= #Tp p_in[31:24];
+ data[63:56] <= p_in[31:24];
if (byte_sel[2])
- data[55:48] <= #Tp p_in[23:16];
+ data[55:48] <= p_in[23:16];
if (byte_sel[1])
- data[47:40] <= #Tp p_in[15:8];
+ data[47:40] <= p_in[15:8];
if (byte_sel[0])
- data[39:32] <= #Tp p_in[7:0];
+ data[39:32] <= p_in[7:0];
end
`else
else if (latch[0] && !tip)
begin
`ifdef SPI_MAX_CHAR_8
if (byte_sel[0])
- data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
+ data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0];
`endif
`ifdef SPI_MAX_CHAR_16
if (byte_sel[0])
- data[7:0] <= #Tp p_in[7:0];
+ data[7:0] <= p_in[7:0];
if (byte_sel[1])
- data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
+ data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8];
`endif
`ifdef SPI_MAX_CHAR_24
if (byte_sel[0])
- data[7:0] <= #Tp p_in[7:0];
+ data[7:0] <= p_in[7:0];
if (byte_sel[1])
- data[15:8] <= #Tp p_in[15:8];
+ data[15:8] <= p_in[15:8];
if (byte_sel[2])
- data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
+ data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16];
`endif
`ifdef SPI_MAX_CHAR_32
if (byte_sel[0])
- data[7:0] <= #Tp p_in[7:0];
+ data[7:0] <= p_in[7:0];
if (byte_sel[1])
- data[15:8] <= #Tp p_in[15:8];
+ data[15:8] <= p_in[15:8];
if (byte_sel[2])
- data[23:16] <= #Tp p_in[23:16];
+ data[23:16] <= p_in[23:16];
if (byte_sel[3])
- data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
+ data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24];
`endif
end
`endif
`endif
else
- data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
+ data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
end
endmodule
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top.v b/usrp2/opencores/spi/rtl/verilog/spi_top.v
index 09b2e50e1..071aeefca 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_top.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_top.v
@@ -52,8 +52,6 @@ module spi_top
ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
);
- parameter Tp = 1;
-
// Wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
@@ -142,18 +140,18 @@ module spi_top
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- wb_dat_o <= #Tp 32'b0;
+ wb_dat_o <= 32'b0;
else
- wb_dat_o <= #Tp wb_dat;
+ wb_dat_o <= wb_dat;
end
// Wb acknowledge
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- wb_ack_o <= #Tp 1'b0;
+ wb_ack_o <= 1'b0;
else
- wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
+ wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
end
// Wb error
@@ -163,47 +161,47 @@ module spi_top
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- wb_int_o <= #Tp 1'b0;
+ wb_int_o <= 1'b0;
else if (ie && tip && last_bit && pos_edge)
- wb_int_o <= #Tp 1'b1;
+ wb_int_o <= 1'b1;
else if (wb_ack_o)
- wb_int_o <= #Tp 1'b0;
+ wb_int_o <= 1'b0;
end
// Divider register
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
+ divider <= {`SPI_DIVIDER_LEN{1'b0}};
else if (spi_divider_sel && wb_we_i && !tip)
begin
`ifdef SPI_DIVIDER_LEN_8
if (wb_sel_i[0])
- divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0];
+ divider <= wb_dat_i[`SPI_DIVIDER_LEN-1:0];
`endif
`ifdef SPI_DIVIDER_LEN_16
if (wb_sel_i[0])
- divider[7:0] <= #Tp wb_dat_i[7:0];
+ divider[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8];
+ divider[`SPI_DIVIDER_LEN-1:8] <= wb_dat_i[`SPI_DIVIDER_LEN-1:8];
`endif
`ifdef SPI_DIVIDER_LEN_24
if (wb_sel_i[0])
- divider[7:0] <= #Tp wb_dat_i[7:0];
+ divider[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- divider[15:8] <= #Tp wb_dat_i[15:8];
+ divider[15:8] <= wb_dat_i[15:8];
if (wb_sel_i[2])
- divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16];
+ divider[`SPI_DIVIDER_LEN-1:16] <= wb_dat_i[`SPI_DIVIDER_LEN-1:16];
`endif
`ifdef SPI_DIVIDER_LEN_32
if (wb_sel_i[0])
- divider[7:0] <= #Tp wb_dat_i[7:0];
+ divider[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- divider[15:8] <= #Tp wb_dat_i[15:8];
+ divider[15:8] <= wb_dat_i[15:8];
if (wb_sel_i[2])
- divider[23:16] <= #Tp wb_dat_i[23:16];
+ divider[23:16] <= wb_dat_i[23:16];
if (wb_sel_i[3])
- divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24];
+ divider[`SPI_DIVIDER_LEN-1:24] <= wb_dat_i[`SPI_DIVIDER_LEN-1:24];
`endif
end
end
@@ -212,16 +210,16 @@ module spi_top
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
+ ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
else if(spi_ctrl_sel && wb_we_i && !tip)
begin
if (wb_sel_i[0])
- ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};
+ ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
if (wb_sel_i[1])
- ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
+ ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
end
else if(tip && last_bit && pos_edge)
- ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
+ ctrl[`SPI_CTRL_GO] <= 1'b0;
end
assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
@@ -236,36 +234,36 @@ module spi_top
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
- ss <= #Tp {`SPI_SS_NB{1'b0}};
+ ss <= {`SPI_SS_NB{1'b0}};
else if(spi_ss_sel && wb_we_i && !tip)
begin
`ifdef SPI_SS_NB_8
if (wb_sel_i[0])
- ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
+ ss <= wb_dat_i[`SPI_SS_NB-1:0];
`endif
`ifdef SPI_SS_NB_16
if (wb_sel_i[0])
- ss[7:0] <= #Tp wb_dat_i[7:0];
+ ss[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8];
+ ss[`SPI_SS_NB-1:8] <= wb_dat_i[`SPI_SS_NB-1:8];
`endif
`ifdef SPI_SS_NB_24
if (wb_sel_i[0])
- ss[7:0] <= #Tp wb_dat_i[7:0];
+ ss[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- ss[15:8] <= #Tp wb_dat_i[15:8];
+ ss[15:8] <= wb_dat_i[15:8];
if (wb_sel_i[2])
- ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16];
+ ss[`SPI_SS_NB-1:16] <= wb_dat_i[`SPI_SS_NB-1:16];
`endif
`ifdef SPI_SS_NB_32
if (wb_sel_i[0])
- ss[7:0] <= #Tp wb_dat_i[7:0];
+ ss[7:0] <= wb_dat_i[7:0];
if (wb_sel_i[1])
- ss[15:8] <= #Tp wb_dat_i[15:8];
+ ss[15:8] <= wb_dat_i[15:8];
if (wb_sel_i[2])
- ss[23:16] <= #Tp wb_dat_i[23:16];
+ ss[23:16] <= wb_dat_i[23:16];
if (wb_sel_i[3])
- ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24];
+ ss[`SPI_SS_NB-1:24] <= wb_dat_i[`SPI_SS_NB-1:24];
`endif
end
end
--
cgit v1.2.3
From 806a2de4cdd9794f6fba915e32534fd2a0f31cb5 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Fri, 26 Mar 2010 14:04:22 -0700
Subject: remove timescale junk
get rid of asynchronous resets
fix spelling error
corrected comment
---
usrp2/opencores/spi/rtl/verilog/spi_clgen.v | 7 +++----
usrp2/opencores/spi/rtl/verilog/spi_defines.v | 2 +-
usrp2/opencores/spi/rtl/verilog/spi_shift.v | 9 ++++-----
usrp2/opencores/spi/rtl/verilog/spi_top.v | 20 +++++++++++---------
usrp2/opencores/spi/rtl/verilog/timescale.v | 2 --
5 files changed, 19 insertions(+), 21 deletions(-)
delete mode 100644 usrp2/opencores/spi/rtl/verilog/timescale.v
(limited to 'usrp2/opencores/spi/rtl')
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
index 3f29f6d7f..2d9c34f40 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
@@ -39,7 +39,6 @@
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
-`include "timescale.v"
module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge);
@@ -66,7 +65,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
// Counter counts half period
- always @(posedge clk_in or posedge rst)
+ always @(posedge clk_in)
begin
if(rst)
cnt <= {`SPI_DIVIDER_LEN{1'b1}};
@@ -80,7 +79,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
end
// clk_out is asserted every other half period
- always @(posedge clk_in or posedge rst)
+ always @(posedge clk_in)
begin
if(rst)
clk_out <= 1'b0;
@@ -89,7 +88,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
end
// Pos and neg edge signals
- always @(posedge clk_in or posedge rst)
+ always @(posedge clk_in)
begin
if(rst)
begin
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index 01de2584d..963a680a8 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -137,7 +137,7 @@
`define SPI_TX_2 2
`define SPI_TX_3 3
`define SPI_CTRL 4
-`define SPI_DEVIDE 5
+`define SPI_DIVIDE 5
`define SPI_SS 6
//
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/opencores/spi/rtl/verilog/spi_shift.v
index c8c73706b..ac3bb3f48 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_shift.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_shift.v
@@ -39,7 +39,6 @@
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
-`include "timescale.v"
module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
@@ -87,7 +86,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
- always @(posedge clk or posedge rst)
+ always @(posedge clk)
begin
if(rst)
cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}};
@@ -101,7 +100,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
end
// Transfer in progress
- always @(posedge clk or posedge rst)
+ always @(posedge clk)
begin
if(rst)
tip <= 1'b0;
@@ -112,7 +111,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
end
// Sending bits to the line
- always @(posedge clk or posedge rst)
+ always @(posedge clk)
begin
if (rst)
s_out <= 1'b0;
@@ -121,7 +120,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
end
// Receiving bits from the line
- always @(posedge clk or posedge rst)
+ always @(posedge clk)
begin
if (rst)
data <= {`SPI_MAX_CHAR{1'b0}};
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top.v b/usrp2/opencores/spi/rtl/verilog/spi_top.v
index 071aeefca..8289449a9 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_top.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_top.v
@@ -1,3 +1,6 @@
+
+// Modified 2010 by Matt Ettus to remove old verilog style
+
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
@@ -40,7 +43,6 @@
`include "spi_defines.v"
-`include "timescale.v"
module spi_top
(
@@ -99,7 +101,7 @@ module spi_top
wire last_bit; // marks last character bit
// Address decoder
- assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE);
+ assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DIVIDE);
assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1);
@@ -130,14 +132,14 @@ module spi_top
`endif
`endif
`SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
- `SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
+ `SPI_DIVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
`SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
default: wb_dat = 32'bx;
endcase
end
// Wb data out
- always @(posedge wb_clk_i or posedge wb_rst_i)
+ always @(posedge wb_clk_i)
begin
if (wb_rst_i)
wb_dat_o <= 32'b0;
@@ -146,7 +148,7 @@ module spi_top
end
// Wb acknowledge
- always @(posedge wb_clk_i or posedge wb_rst_i)
+ always @(posedge wb_clk_i)
begin
if (wb_rst_i)
wb_ack_o <= 1'b0;
@@ -158,7 +160,7 @@ module spi_top
assign wb_err_o = 1'b0;
// Interrupt
- always @(posedge wb_clk_i or posedge wb_rst_i)
+ always @(posedge wb_clk_i)
begin
if (wb_rst_i)
wb_int_o <= 1'b0;
@@ -169,7 +171,7 @@ module spi_top
end
// Divider register
- always @(posedge wb_clk_i or posedge wb_rst_i)
+ always @(posedge wb_clk_i)
begin
if (wb_rst_i)
divider <= {`SPI_DIVIDER_LEN{1'b0}};
@@ -207,7 +209,7 @@ module spi_top
end
// Ctrl register
- always @(posedge wb_clk_i or posedge wb_rst_i)
+ always @(posedge wb_clk_i)
begin
if (wb_rst_i)
ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
@@ -231,7 +233,7 @@ module spi_top
assign ass = ctrl[`SPI_CTRL_ASS];
// Slave select register
- always @(posedge wb_clk_i or posedge wb_rst_i)
+ always @(posedge wb_clk_i)
begin
if (wb_rst_i)
ss <= {`SPI_SS_NB{1'b0}};
diff --git a/usrp2/opencores/spi/rtl/verilog/timescale.v b/usrp2/opencores/spi/rtl/verilog/timescale.v
deleted file mode 100644
index 60d4ecbd1..000000000
--- a/usrp2/opencores/spi/rtl/verilog/timescale.v
+++ /dev/null
@@ -1,2 +0,0 @@
-`timescale 1ns / 10ps
-
--
cgit v1.2.3
From cce4104964c1e1930f85dbb0bb8b8f33086bd75e Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Sat, 27 Mar 2010 09:20:50 -0700
Subject: 16 bit wide spi core
---
usrp2/opencores/spi/rtl/verilog/spi_top16.v | 182 ++++++++++++++++++++++++++++
1 file changed, 182 insertions(+)
create mode 100644 usrp2/opencores/spi/rtl/verilog/spi_top16.v
(limited to 'usrp2/opencores/spi/rtl')
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top16.v b/usrp2/opencores/spi/rtl/verilog/spi_top16.v
new file mode 100644
index 000000000..ee808a8ab
--- /dev/null
+++ b/usrp2/opencores/spi/rtl/verilog/spi_top16.v
@@ -0,0 +1,182 @@
+
+// Modified 2010 by Matt Ettus to remove old verilog style and
+// allow 16-bit operation
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// spi_top.v ////
+//// ////
+//// This file is part of the SPI IP core project ////
+//// http://www.opencores.org/projects/spi/ ////
+//// ////
+//// Author(s): ////
+//// - Simon Srot (simons@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+`include "spi_defines.v"
+
+module spi_top16
+ (input wb_clk_i, input wb_rst_i,
+ input [4:0] wb_adr_i,
+ input [15:0] wb_dat_i,
+ output reg [15:0] wb_dat_o,
+ input [1:0] wb_sel_i,
+ input wb_we_i, input wb_stb_i, input wb_cyc_i,
+ output reg wb_ack_o, output wb_err_o, output reg wb_int_o,
+
+ // SPI signals
+ output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i);
+
+ // Internal signals
+ reg [15:0] divider; // Divider register
+ reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register
+ reg [15:0] ss; // Slave select register
+ reg [31:0] wb_dat; // wb data out
+ wire [31:0] rx; // Rx register
+ wire rx_negedge; // miso is sampled on negative edge
+ wire tx_negedge; // mosi is driven on negative edge
+ wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len
+ wire go; // go
+ wire lsb; // lsb first on line
+ wire ie; // interrupt enable
+ wire ass; // automatic slave select
+ wire spi_divider_sel; // divider register select
+ wire spi_ctrl_sel; // ctrl register select
+ wire [3:0] spi_tx_sel; // tx_l register select
+ wire spi_ss_sel; // ss register select
+ wire tip; // transfer in progress
+ wire pos_edge; // recognize posedge of sclk
+ wire neg_edge; // recognize negedge of sclk
+ wire last_bit; // marks last character bit
+
+ // Address decoder
+ assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE);
+ assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL);
+ assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0);
+ assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1);
+ assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2);
+ assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3);
+ assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);
+
+ always @(wb_adr_i or rx or ctrl or divider or ss)
+ case (wb_adr_i[4:2])
+ `SPI_RX_0: wb_dat = rx[31:0];
+ `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
+ `SPI_DIVIDE: wb_dat = {16'b0, divider};
+ `SPI_SS: wb_dat = {16'b0, ss};
+ default : wb_dat = 32'd0;
+ endcase // case (wb_adr_i[4:2])
+
+ always @(posedge wb_clk_i)
+ if (wb_rst_i)
+ wb_dat_o <= 32'b0;
+ else
+ wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0];
+
+ always @(posedge wb_clk_i)
+ if (wb_rst_i)
+ wb_ack_o <= 1'b0;
+ else
+ wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
+
+ assign wb_err_o = 1'b0;
+
+ // Interrupt
+ always @(posedge wb_clk_i)
+ if (wb_rst_i)
+ wb_int_o <= 1'b0;
+ else if (ie && tip && last_bit && pos_edge)
+ wb_int_o <= 1'b1;
+ else if (wb_ack_o)
+ wb_int_o <= 1'b0;
+
+ // Divider register
+ always @(posedge wb_clk_i)
+ if (wb_rst_i)
+ divider <= 16'b0;
+ else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1])
+ divider <= wb_dat_i;
+
+ // Ctrl register
+ always @(posedge wb_clk_i)
+ if (wb_rst_i)
+ ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
+ else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1])
+ begin
+ if (wb_sel_i[0])
+ ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
+ if (wb_sel_i[1])
+ ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
+ end
+ else if(tip && last_bit && pos_edge)
+ ctrl[`SPI_CTRL_GO] <= 1'b0;
+
+ assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
+ assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
+ assign go = ctrl[`SPI_CTRL_GO];
+ assign char_len = ctrl[`SPI_CTRL_CHAR_LEN];
+ assign lsb = ctrl[`SPI_CTRL_LSB];
+ assign ie = ctrl[`SPI_CTRL_IE];
+ assign ass = ctrl[`SPI_CTRL_ASS];
+
+ // Slave select register
+ always @(posedge wb_clk_i)
+ if (wb_rst_i)
+ ss <= 16'b0;
+ else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1])
+ begin
+ if (wb_sel_i[0])
+ ss[7:0] <= wb_dat_i[7:0];
+ if (wb_sel_i[1])
+ ss[15:8] <= wb_dat_i[15:8];
+ end
+
+ assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}}));
+
+ spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
+ .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
+ .neg_edge(neg_edge));
+
+ wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]),
+ (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) };
+
+
+ spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
+ .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb),
+ .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
+ .rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
+ .tip(tip), .last(last_bit),
+ .p_in({wb_dat_i,wb_dat_i}), .p_out(rx),
+ .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
+
+endmodule // spi_top16
--
cgit v1.2.3